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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sta Engineer - Top Level (Senior) - **Company:** Hireroo - **Location:** Barcelona, Spain - **Contract:** Permanent contract - **Skills:** Computer Engineering, Firmware, Python (Programming Language), PCI Express, Static Timing Analysis, Tcl (Programming Language), Working Model 2D, Scripting, Application Specific Integrated Circuits, Physical Design - **Published:** September 27, 2026 - **Apply:** https://www.buscojobs.com.es/sta-engineer-top-level-senior-en-barcelona-ID-373558093 ## About the Role Senior level experience in static timing analysis - Strong experience with top level timing constraints - Strong knowledge of SDC and timing exceptions - Experience with clock and reset strategy - Experience supporting timing closure for SoC or complex ASIC designs - Familiarity with physical implementation flows - Strong scripting skills, Tcl, Python or Shell - Experience with EDA timing tools - English level C1 - Bachelor, Master or PhD in Electrical Engineering, Microelectronics, Computer Engineering or related field Preferred / Valued knowledge: - Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments. ## Description Job Description Our client is expanding their Physical Design and timing function and is looking for a Senior STA Engineer, Top Level to support timing constraints and timing closure across complex SoC designs.In this role, you will create, review and verify block and top level timing constraints.You will work closely with physical implementation, RTL, verification and architecture teams to ensure clean and reliable timing closure for advanced semiconductor programs.Location : Barcelona, Spain - Hybrid Responsibilities: As a Senior STA Engineer, Top Level, your broad responsibilities will include but are not limited to:- Create and verify block and top level timing constraints- Support static timing analysis across complex SoC designs- Work with implementation teams to resolve timing issues- Define and review SDC constraints- Support clock strategy, reset strategy and timing exceptions- Collaborate with RTL, physical implementation and architecture teams- Analyze timing reports and drive closure actions- Contribute to timing methodology improvements- Support tape out readiness from a timing perspective Requirements:- Senior level experience in static timing analysis- Strong experience with top level timing constraints- Strong knowledge of SDC and timing exceptions- Experience with clock and reset strategy- Experience supporting timing closure for SoC or complex ASIC designs- Familiarity with physical implementation flows- Strong scripting skills, Tcl, Python or Shell- Experience with EDA timing tools- English level C1- Bachelor, Master or PhD in Electrical Engineering, Microelectronics, Computer Engineering or related field Preferred / Valued knowledge:- Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments.What's in it for you?Our client offers an exciting, challenging role in a collaborative, dynamic environment.The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future.Benefits: Flexible working hours(office open between 7 AM and 9 PM, employees manage their own schedule) Hybrid working model One week per year work from anywhere 25 days annual leave plus December 24 and 31 €150 per month food allowance (? €**** per year additional compensation) Private medical insurance One time relocation bonus paid with the first salary Support with housing search through an agency Visa support if required Relocation support for family Virtual shares Language classes(Spanish, English, Catalan) Tax incentive ## Related Videos - [Why Your Best Mediors Never Become Seniors (And How to Fix It)](https://www.wearedevelopers.com/videos/2108-why-your-best-mediors-never-become-seniors-and-how-to-fix-it) - [JavaScript? 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