> Markdown version of [/jobs/ext/3139342-asic-engineer-i-annapurna-labs-early-career-2027](https://www.wearedevelopers.com/jobs/ext/3139342-asic-engineer-i-annapurna-labs-early-career-2027). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# ASIC Engineer I, Annapurna Labs, Early Career - 2027

- **Company:** Amazon.com, Inc.
- **Location:** Austin, TX, United States
- **Salary:** $116,100.0
- **Contract:** Internship / Graduate position
- **Skills:** Very-Large-Scale Integration, Boolean Algebra, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Perl (Programming Language), Hardware Description Language, Hardware Design, Python (Programming Language), Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, State Machines, Information Technology, Physical Design
- **Published:** September 29, 2026
- **Apply:** https://dejobs.org/x/x/B199CB9073B74D17869DCD337125EC86/job/

## About the Role

* Bachelor's or Master's degree program in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with a final graduation date of May 2027 or earlier
 * Coursework or project experience in digital logic design and computer architecture
 * Familiarity with a hardware description language (Verilog, SystemVerilog, or VHDL)
 * Understanding of fundamental digital design concepts: combinational and sequential logic, finite state machines, timing, and clocking, * Bachelor's or Master's degree with a focus on VLSI, digital design, or computer architecture
 * Experience with industry-standard EDA tools (Cadence, Synopsys, or equivalent)
 * Scripting experience (Python, Perl, TCL, or shell) for automation and design flows
 * Prior internship, research, or lab experience in chip design, embedded systems, or hardware development

## Description

As an ASIC Engineer I, you'll contribute to real chip development work, which may include:

 * Designing and implementing RTL for digital logic blocks using Verilog/SystemVerilog
 * Developing and running verification environments to validate design functionality and coverage
 * Supporting synthesis, timing analysis, and physical design flows
 * Debugging design issues through simulation and analysis
 * Collaborating with architecture, verification, and physical design teams to take features from specification to silicon
 * Documenting your design decisions and presenting your work to the team