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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Applications Engineering, Sr Staff Engineer - **Company:** Synopsys - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $157,000.0 - $235,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Computer Engineering, Ethernet, Field-Programmable Gate Array (FPGA), Python (Programming Language), Machine Learning, PCI Express, Shell Script, SystemVerilog, Tcl (Programming Language), USB, Vivado, Application Specific Integrated Circuits, Information Technology, Physical Design - **Published:** September 16, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=4a61f2487aebae6b ## About the Role * Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience * 10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation * Deep expertise in FPGA synthesis, place-and-route, multi-FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools * Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture * Hands-on experience with interface IP including PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or high-speed SerDes protocols * Proficiency in Tcl, Python, or shell scripting for automation and flow development * Direct experience with Synopsys HAPS and ProtoCompiler is a strong plus, as is experience with ZeBu, Palladium, Protium, or Veloce emulation platforms ## Description * You can walk into a room with a customer's architecture team, understand their SoC in an hour, and identify the three partitioning decisions that will make or break their prototype schedule * When a PCIe link will not train or a DDR interface fails calibration, you know where to look first and how to instrument the design to prove your hypothesis * You are comfortable presenting technical tradeoffs to VPs and engineering directors without oversimplifying the problem or losing the nuance that matters * You do not wait for perfect information or complete documentation. You dig into logs, RTL, netlists, and hardware captures to figure out what is actually happening * You have debugged designs using Verdi, runtime instrumentation, protocol analyzers, or assertion-based techniques and can teach others how to do the same * You can explain why emulation and prototyping solve different problems, and you have the technical depth to back up that explanation with real architectural tradeoffs The Team You'll Be Part Of You will join the Hardware-Assisted Verification (HAV) organization, working closely with Applications Engineers, R&D, Product Management, Sales, and Customer Success teams globally. This is a highly visible role supporting strategic semiconductor, hyperscaler, AI/ML, automotive, and aerospace customers deploying HAPS-200, ProtoCompiler, and the broader Synopsys verification ecosystem. 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