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# Senior Engineer Digital IP iv)

- **Company:** Infineon Technologies AG
- **Location:** Dresden, Germany
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Unix, Computer Engineering, Software Debugging, Microsoft Office, Perforce, Software Tools, Systems Architecture, SystemVerilog, Universal Asynchronous Receiver/Transmitter, Verilog, Serial Peripheral Interface, Git, Software Version Control
- **Published:** September 1, 2026
- **Apply:** https://de.indeed.com/viewjob?jk=4b29b3e3f5577658

## About the Role

* Bachelor's or master's degree in electrical engineering, Electronics Engineering, Computer Engineering, or a related field.
 * 3+ years of experience in semiconductor digital IP design and RTL development, with strong hands-on execution.
 * Proven expertise RTL coding, design documentation, RTL release execution, and integration support.
 * Strong proficiency in System Verilog and Verilog.
 * Knowledge of commonly used bus protocols such as AHB/APB is a plus.
 * Practical experience with Lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related design quality flows.
 * Experience with automated, configurable, or generator-based RTL development flows for IP creation, integration, and release preparation.
 * Strong interest in applying AI-assisted engineering tools to improve RTL development, integration, debug, documentation, automation, quality closure, and release readiness.
 * Working knowledge of UNIX and Windows environments, MS Office tools, and version control systems such as Git or Perforce.
 * Proactive and collaborative approach to risk identification, issue resolution, and stakeholder communication.

## Description

* Hands-on digital IP design execution, RTL implementation, design documentation, integration support, and release readiness.
 * Develop high-quality RTL in System Verilog/Verilog for reusable, configurable, and integration-ready IP blocks.
 * Drive design quality closure through Lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related sign-off activities.
 * Debug and resolve block-level, integration-level, and system-level design issues in close collaboration with Verification and Architecture.
 * Support development and integration of communication and peripheral IPs such as I2C, UART, SPI, AHB/APB-based interfaces, and similar digital IP blocks.
 * Work with automated, configurable, and generator-based RTL development flows to improve reuse, scalability, consistency, and design productivity.
 * Establish and follow robust design processes, quality gates, and release practices to minimize bug escapes from the IP qualification flow.
 * This position is limited to 21 months


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