> Markdown version of [/jobs/ext/3234168-research-associate-heterogeneous-integration-systems-architecture-and-design](https://www.wearedevelopers.com/jobs/ext/3234168-research-associate-heterogeneous-integration-systems-architecture-and-design). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Research Associate - Heterogeneous Integration: Systems Architecture and Design - **Company:** University of Sheffield - **Location:** Sheffield, UK - **Salary:** £38,784.0 - £47,389.0 - **Contract:** Temporary contract - **Skills:** Artificial Intelligence, Software Applications, Application Services, Systems Engineering, Architectural Patterns, Computer Engineering, Field-Programmable Gate Array (FPGA), Internet Message Access Protocols, Interoperability, Open Source Technology, Reduced Instruction Set Computing, Systems Architecture, System on a Chip, Digital Twin, Information Technology, Front End Software Development - **Published:** September 18, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=a11a66f433bc4467 ## About the Role We offer a fantastic range of benefits including a highly competitive annual leave entitlement (with the ability to purchase more), a generous pensions scheme, flexible working opportunities, a commitment to your development and wellbeing, a wide range of retail discounts, and much more. ## Description * It is a national-programme intelligence role. You will lead landscape and roadmap work that directly shapes CHIMES² research priorities, demonstrator projects, and the Design Commons - work with reach across the UK ecosystem, not confined to a single lab. * It is a deliberate platform to launch from. The post is designed to let you build a visible, fundable independent research identity and the track record to launch it - whether toward a research fellowship (RAEng, UKRI FLF, MSCA, ERC Starting), a first permanent academic appointment, or a senior role in the national semiconductor ecosystem. The four-year term gives genuine room to figure out which of those is right for you and to become competitive for it. * You will be a named representative of CHIMES² externally - at IMAPS, IEEE ECTC, DATE, Hot Chips, TechWorks DESN and equivalent forums - and a named author on Design Commons white papers, capability maps and policy briefings produced from your work. Areas of particular interest for this post include: * System partitioning and chiplet decomposition methodologies; cross-die interface specification frameworks. * System-technology co-optimisation (STCO/XTCO) and mission-aware partitioning under power, thermal and security constraints. * Front-end and system-level EDA for multi-die design - partition-aware synthesis, architectural exploration, system-level floor planning, cross-die timing, die-to-die interface IP. * Chiplet interconnect standards (UCIe, CXL, die-to-die PHY) and interoperability frameworks (3Dblox, OIF). * Open Design Commons infrastructure and open-source EDA / RISC-V IP ecosystems. All four cross-cutting constraints - design-for-test (DfT), design-for-power-delivery (DfP), design-for-security (DfS) and design-for-thermal-extraction (DfTh) - span the logical-physical boundary, and both post holders are expected to develop working familiarity with them regardless of primary domain. No candidate need span all areas. Strong credibility in logical systems architecture and front-end design is the core requirement; depth in one or more of the complementary areas above is welcomed. We particularly welcome applicants whose work has bridged from adjacent backgrounds - computer architecture, embedded systems, FPGA-based research, accelerator or hardware-software co-design, low-power or sensor or quantum-hardware systems, or high-speed PCB / board-level integration - into circuit, system and integration work. To be clear, the focus is on the systems-and-integration direction; candidates whose current work is still on the device-physics or process side are out of scope for this post, as that capability is well covered elsewhere in the QSS Group, through CHIMES² partners (notably Imec), and through national semiconductor programmes. Main duties and responsibilities Technology landscape and roadmap * Lead the WP1 logical systems architecture domain landscape activities - structured analysis of the needs of integrators and of those seeking to integrate maturing-TRL device, circuit or interposer propositions - covering system partitioning, chiplet decomposition, cross-die interface specification, and STCO/XTCO approaches across the UK and international HI community. * Develop and maintain CHIMES² roadmaps for the logical architecture and front-end design domain, cross-referencing international roadmap assets including IEEE HIR, EU APECS, DARPA CHIPS/NGMM, SRC JUMP 2.0, imec STCO, and interoperability standards (UCIe / 3Dblox / OIF / CXL). * Analyse front-end EDA tool gaps for heterogeneous integration - partition-aware synthesis, multi-die timing closure, DfT insertion at the chiplet boundary, DfS architectural patterns, power-intent specification across dies (UPF/CPF), and thermal-aware floorplanning. * Conduct structured gap analysis identifying integration-specific design challenges underserved by current UK and international R&D, particularly in multi-vendor chiplet EDA flows, STCO, and open Design Commons infrastructure. Leadership and ecosystem engagement * Represent CHIMES² at national and international events and policy forums (IMAPS, IEEE ECTC, TechWorks DESN, DATE, Hot Chips and equivalent), and build relationships across the design, EDA, foundry/OSAT and standards communities (IEEE, JEDEC, IPC, SEMI, UCIe Consortium). * Contribute technical intelligence to CHIMES² business and policy development - government consultation responses, policy briefings, and the programme's strategic positioning - and communicate landscape findings to the Advisory and Technical Advisory Boards. * Work collaboratively with domain-specific PDRAs recruited by CHIMES² Co-Investigators, aggregating contributions across the research college into coherent programme-level roadmap assets, and collaborate with the companion RIF on the logical-to-physical handoff methodology. * Work closely with the CHIMES² Sheffield engineering team, contributing CTO Office intelligence to Design Commons and demonstrator delivery and to the programme's skills-building activities. Knowledge asset creation * Lead the development of Design Commons white papers, capability maps and curated landscape reports in your domain, translating complex technical and ecosystem intelligence into outputs accessible to both technical and policy audiences. * Apply and help shape the CHIMES² roadmapping methodology (technology roadmapping, systems thinking, gap analysis), ensuring outputs align with international benchmarks (IEEE HIR, EU Chips JU, DARPA NGMM, SRC JUMP 2.0). * Contribute to co-created WP3 demonstrator project briefs and to Annual Reports, milestone deliverables and Flexible Funding call documentation. Research, authorship and translation * Develop an independent research theme arising from your landscape and roadmap work, with protected time agreed in the workplan at appointment and signed off by the CHIMES² Director. This theme is expected to intersect with CHIMES²'s heterogeneous-integration mission and to form the basis of future fellowship or first-academic-post applications. * Be a named author on CHIMES² Design Commons white papers, capability maps and policy briefings, supported to develop these into peer-reviewed outputs and conference presentations. * Collaborate with Co-Investigators and PDRAs to keep landscape work grounded in current research frontiers, and contribute to future funding applications and programme extensions. * Carry out other duties, commensurate with the grade and remit of the post Person Specification Our community welcomes diverse backgrounds and experiences. We particularly encourage applications from researchers in their first postdoctoral position, and from researchers in a second postdoctoral role who would prefer a post of this kind to moving directly to a lectureship and from candidates whose work has bridged from adjacent backgrounds (materials, devices, sensors, photonics, RF, quantum hardware, FPGA, embedded systems, or high-speed PCB / board-level integration) into circuit, system and integration work. Even if your past experience doesn't match perfectly with this role's criteria, your contribution is valuable and we encourage you to apply. Please ensure that you reference the application criteria in your application statement. Applicants must provide the following documents when making their application - please upload a merged PDF document under the cover letter section on our application system: * CV (including a list of publications and / or technical outputs). * A Research Vision Statement, setting out the independent research direction you would develop in this post and how it intersects with CHIMES²'s heterogeneous-integration mission - written so that it could form the seed of a future fellowship or first-academic-post application. * A statement of up to three best outputs (peer-reviewed publications, or for candidates from industry, technical reports, standards contributions, or product / roadmap documentation that demonstrate the ability to produce high-quality written intelligence). For one of these, provide a short statement of no more than 100 words describing its originality, significance and rigour. Key selection criteria include: * Technical credibility in the logical systems architecture and front-end design domain (the primary shortlisting filter). * Ability to synthesise and communicate complex technical intelligence to specialist and non-specialist audiences (the primary differentiator at interview, alongside technical depth). * A credible, articulated independent research vision that intersects with CHIMES²'s mission. * Ability to work across academic and industrial environments and to represent a national programme externally. The full criteria are listed in the table below. No candidate need span all areas: we are looking for strength in the core domain competence plus depth in one or more of the named complementary areas. Criteria Essential or desirable Stage(s) assessed at Completed (or near completion of) a PhD in electrical and electronic engineering, computer engineering, computer science or a closely related discipline, with demonstrable expertise in one or more of: IC or SoC design; digital or mixed-signal EDA; heterogeneous integration or advanced packaging; chiplet architecture; or hardware-software co-design. Equivalent industrial R&D experience is also considered. Essential Application Knowledge of logical systems architecture for heterogeneous integration - system partitioning, chiplet decomposition, cross-die interface specification, and front-end EDA flows (RTL, synthesis, floorplanning, partition-aware timing) - and of how logical decisions determine downstream physical implementation and manufacturing requirements. Essential Application & Interview Familiarity with at least one front-end or system-level EDA domain relevant to HI: multi-die architectural exploration tools (Synopsys 3DIC Compiler, Cadence Integrity 3D-IC, Siemens Innovator3D-IC); STCO/XTCO methodology; UCIe / CXL / other die-to-die interconnect standards; open-source EDA (OpenROAD, OpenLane, RISC-V IP); or DfT / DfS methodologies at the multi-chiplet level. Essential Application & Interview Awareness of the four cross-cutting constraints spanning the logical-physical boundary - DfT (e.g. IEEE 1838 3D-IC test, known-good-die implications), DfP (UPF/CPF power intent, IVR strategies, backside power delivery), DfS (hardware root-of-trust, chiplet attestation, secure supply chain, side-channel considerations) and DfTh (thermal-aware floorplanning, TIM selection, embedded cooling, junction-temperature budgeting). Working familiarity with all four is expected regardless of primary specialism. Desirable Application & Interview Demonstrable ability to synthesise complex technical and ecosystem intelligence into high-quality written outputs accessible to technical and non-specialist audiences - policy briefings, landscape reports, capability maps, white papers, or equivalent industry deliverables. Industry candidates may evidence this through technical reports, roadmap documentation or standards contributions. Essential Application & Interview A credible, articulated independent research vision that intersects with (rather than runs parallel to) CHIMES²'s heterogeneous-integration mission, with the potential to develop into fellowship or first-academic-post applications. Essential Application & Interview Participation in silicon tape-out or equivalent design-cycle experience - recognised through MPW programmes (Europractice, eFabless, TinyTapeout) or through industrial product development. Desirable Application & Interview Experience applying AI/ML to EDA workflows, digital-twin approaches, or model-based systems engineering applied to heterogeneous integration. Desirable Application & Interview Evidence of external engagement - conference presentations, cross-institution collaboration, or equivalent industry engagement - and the ability to represent an organisation professionally in technical and policy forums. Desirable Application & Interview Active engagement in external networks, consortia or working groups, contributing to jointly authored recommendations, standards submissions, roadmap assets or other collective outputs. Desirable Application & Interview Strong written and verbal communication; ability to work independently across multiple workstreams; ability to work across academic and industrial environments; commitment to equality, diversity and inclusion. Essential Application & Interview Familiarity with the UK and international semiconductor policy landscape (UKRI IKC model, National Semiconductor Strategy, EU Chips Act, US CHIPS & Science Act) and with UKRI-funded networks, hubs or centres. Desirable Application & Interview Experience of mentoring, supervising or line-managing early-career researchers or PGR students. Desirable Application & Interview Track record of contributing to successful external research funding applications, as named investigator or equivalent. Candidates from industry may evidence this through authorship of successful internal investment cases, product or programme proposals, or change proposals that secured funding, headcount or executive approval. Desirable Application & Interview Experience of representing an organisation at national or international level in policy, standards or advisory forums - government consultations, advisory boards, standards bodies, or equivalent industry and professional groupings. Desirable Application & Interview Further Information Grade 7 ## Related Videos - [Code to Road in < 12 hours](https://www.wearedevelopers.com/videos/1082-code-to-road-in-12-hours) - [HR & Tech: Why can't we be friends?](https://www.wearedevelopers.com/videos/1493-hr-tech-why-can-t-we-be-friends) - [From Bedside Beeps to Interoperable Bytes – Getting your medical devices ready to talk the IEEE 11073 language](https://www.wearedevelopers.com/videos/771-from-bedside-beeps-to-interoperable-bytes-getting-your-medical-devices-ready-to-talk-the-ieee-11073-language) - [AI in Regulated Industry - Validating AI-Enabled Products with PLM and Digital Twins](https://www.wearedevelopers.com/videos/2065-ai-in-regulated-industry-validating-ai-enabled-products-with-plm-and-digital-twins) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Goodbye Microservices, Hello Self-Contained Systems](https://www.wearedevelopers.com/videos/100009-goodbye-microservices-hello-self-contained-systems) ## Related Articles - [Data Engineer Salary UK](https://www.wearedevelopers.com/magazine/253-data-engineer-salary-uk) - [Software Engineer Salary in The UK](https://www.wearedevelopers.com/magazine/231-software-engineer-salary-in-the-uk) - [The 12 Best Jobs for Software Engineers](https://www.wearedevelopers.com/magazine/401-the-12-best-jobs-for-software-engineers) - [Software Engineer Salary London](https://www.wearedevelopers.com/magazine/252-software-engineer-salary-london) - [Top-Paying Tech Jobs (with Salaries)](https://www.wearedevelopers.com/magazine/372-top-paying-tech-jobs-with-salaries) - [IT Salaries in UK](https://www.wearedevelopers.com/magazine/288-it-salaries-in-uk)