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# Senior Reliability PDK and TFM engineer

- **Company:** Intel Corporation
- **Location:** Phoenix, AZ, United States
- **Experience:** Expert
- **Salary:** $149,600.0 - $284,580.0
- **Contract:** Internship / Graduate position
- **Skills:** Artificial Intelligence, System on a Chip
- **Published:** September 10, 2026
- **Apply:** https://www.phoenixjobs.com/job.asp?id=3385167673&tx=FL333FFP&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Excellent written and verbal communication and presentation skills.
 * Passion for quality and attention for details and procedures, looking for opportunities to drive efficiency and innovations.
 * Demonstrated capability to drive quality enhancements projects.
 * Strong team player with proven ability to work in diverse multi-cultural environment. Must be flexible and adaptable to ensure program commitments are met on time in a dynamic work environment., * Bachelor's degree in electrical engineering, physics or a related field and 6+ years of relevant work experience or 4+ years of relevant experience and a master's degree, or a PhD degree with 2+ years of relevant experience.
 * 3+ years' experience in one of the following areas: PDK development, reliability tool and flow, design for reliability, Circuit, IP and SOC design reliability validation using PDK, EDA tool and flow development., * Master's degree in electrical engineering, physics, or related field, or Ph.D. degree in electrical engineering, physics, or related fields.
 * Hands-on Experience on PDK development and validation; knowledge and understanding of PDK fundamentals; reliability design rules and their implementation in PDK and TFM. Capability to use AI or program skills to write code, agent or script for design rule, techfile generation and quality assurance.
 * Experience on PDK, EDA tool/flow development, design flow application and interaction with IP and SOC design validation and sign-off; design impact and risk assessment in related reliability area.
 * Experience and knowledge on reliability verification and physics, such as aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, high voltage design, EOS (Electrical Over-Stress), ESD (Electrostatic Discharge).
 * Experiences and skills in program management, stakeholder management, and strong communication skills.

Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences., Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here (https://jobs.intel.com/benefits) : https://jobs.intel.com/benefits

## Description

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.


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