> Markdown version of [/jobs/ext/3275459-lead-software-engineer-low-power-verification](https://www.wearedevelopers.com/jobs/ext/3275459-lead-software-engineer-low-power-verification). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Lead Software Engineer - Low Power Verification - **Company:** Cadence Design Systems, Inc. - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $114,800.0 - $213,200.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, C++ (Programming Language), Cursor, Software Debugging, Event Logging, SystemVerilog, Test Case, Verilog, VHSIC Hardware Description Language (VHDL) - **Published:** September 15, 2026 - **Apply:** https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Lead-Software-Engineer---Low-Power-Verification_R56210 ## About the Role * BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience. * Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL). * Strong debugging skills - root-cause analysis from logs, waveforms, traces, testcases, and user reports. * Ability to read, review, and reason about C++ code and object-oriented designs. * Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output. * Strong communication and technical writing skills - able to turn scattered debug evidence into clear, user-facing workflows. ## Description * Enhance UPF debug features -- improve performance and usability across the Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support. * Scale UPF event logging and violation detection - apply new techniques to capture and report more UPF events, with better multi-billion-gate low-power designs. * Rebuild UPF documentation around end-to-end debug scenarios and workflows, backed by valid SystemVerilog and UPF examples. * Help develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues. * Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state). * Help consolidate and unify UPF debug across Palladium and Protium.