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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior FPGA Engineer - **Company:** TalentBridge - **Location:** Chandler, AZ, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Address Resolution Protocols, C++ (Programming Language), Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Linux on Embedded Systems, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Internet Control Message Protocol, Internet Group Management Protocols, IPv4, IPv6, Transport Layer, Linux Kernel, Microsoft Office, PCI Express, Satcom, Zero Trust Network Access, Schematic Capture, Static Timing Analysis, System on a Chip, SystemVerilog, Transmission Control Protocol (TCP), VHSIC Hardware Description Language (VHDL), IEEE 802.3, Vivado, Application Specific Integrated Circuits, Hardware Testing, Git, Yocto, Evolved Common Public Radio Interface (eCPRI), U-Boot - **Published:** September 1, 2026 - **Apply:** https://www.dice.com/job-detail/a196c288-027a-4116-956d-27b9abc06295 ## About the Role * Strong digital design experience with FPGA/ASIC SoC development. * Hands-on FPGA implementation experience using Client (Altera) Quartus or Xilinx Vivado. * Experience designing and debugging SoC systems utilizing AMBA AXI and APB interfaces. * Experience developing high-throughput, pipelined AXI-Stream IP optimized for performance. * Ability to create RTL simulations to identify and resolve issues prior to hardware testing. * Strong understanding of Static Timing Analysis (STA) and Synopsis Design Constraints (SDC). * Experience analyzing timing reports and post-synthesis placement/routing to resolve timing violations. * Experience contributing to FPGA portions of PCB schematic capture and board layout. * Experience implementing at least one high-speed serial protocol, such as: + PCI Express + Interlaken, + Layer 1: IEEE 802.3 Ethernet standards (1G-100G) + Layer 2/3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP + Layer 4: VITA 49.2, DIFI, and/or eCPRI (highly preferred) * Proficiency in: + C + C++ + Git version control * Strong Microsoft Office skills. * Experience supporting cross-functional engineering teams. Preferred Qualifications * Knowledge of digital IF standards including VITA 49.2, DIFI, or eCPRI. * Experience with Embedded Linux, including: + Linux Kernel + Yocto + U-Boot + Device Tree * Familiarity with SATCOM waveforms such as: + DVB-S2X + 5G NTN (3GPP Release 17/18) * Understanding of secure communications and Zero Trust architectures. * Experience with: + Partial Reconfiguration (DFX) + PCIe CvP * Active DoD Security Clearance or ability to obtain one. Education * Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. Experience * 5+ years of FPGA/ASIC SoC design experience. ## Description We are seeking a Senior FPGA Engineer with experience across the entire design flow for complex FPGAs to lead the design, development, and debugging of FPGA SoC systems supporting advanced satellite communications technologies. This role focuses on advanced IP integration, high-performance RTL development, and userspace driver/firmware development., * Design, develop, document, debug, and test FPGA SoC systems, including: + IP integration into FPGA projects (synthesis and implementation) + High-performance FPGA IP development (VHDL/SystemVerilog) + Userspace drivers for FPGA IP (C++) + Firmware for embedded microcontrollers (C) * Collaborate effectively with engineering teams and leadership throughout the development lifecycle. * Support the design, implementation, validation, and optimization of complex FPGA solutions. ## Related Videos - [IP Authentication: A Tale of Performance Pitfalls and Challenges in Prod](https://www.wearedevelopers.com/videos/1413-ip-authentication-a-tale-of-performance-pitfalls-and-challenges-in-prod) - [IoT: The road to sustainability](https://www.wearedevelopers.com/videos/557-iot-the-road-to-sustainability) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) ## Related Articles - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [How Much FAANG Companies Actually Pay Software Engineers in 2025](https://www.wearedevelopers.com/magazine/230-how-much-faang-companies-actually-pay-software-engineers-in-2025) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Software Developer Salary in Switzerland [2023]](https://www.wearedevelopers.com/magazine/215-software-developer-salary-in-switzerland-2023)