> Markdown version of [/jobs/ext/3306526-asic-iii-amz27336-4](https://www.wearedevelopers.com/jobs/ext/3306526-asic-iii-amz27336-4). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# ASIC III - AMZ27336.4

- **Company:** Annapurna Labs
- **Location:** Austin, TX, United States
- **Experience:** Experienced
- **Salary:** $202,779.0 - $215,300.0
- **Contract:** Permanent contract
- **Skills:** Amazon Web Services, Code Review, Computer Engineering, Software Debugging, Subsystems, Application Specific Integrated Circuits, Information Technology, Physical Design
- **Published:** September 13, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=afaa02cde4376703

## About the Role

A Master's degree or foreign equivalent in Computer Science, Computer Engineering, Electronics Engineering, or a related field and 5 years of experience in the job offered or a related
occupation. In the alternative, a Bachelor's degree or foreign equivalent in Computer Science, Computer Engineering, Electronics Engineering or a related field followed by 7 years of
progressively responsible post-baccalaureate experience in the job offered or a related occupation.
Must have 3 years of experience in the following:
1) SOC/IO/Subsystems.
2) DDR/HBM at the PHY and controller level and DDR/HBM training, timing parameters and/or controller features.
3) Driving the IP Integration and designing silicon and 2.5D packaging.
4) Supporting the physical design team, reviewing clocking and timing constraints
5) Driving cross-functional triage effort on complex functional and performance issues.
6) Taking the leadership role in post-silicon bring-up of IO and HBM/DRRx stack.
7) Defining boot-up initialization, reset flow, training sequence.
8) Performing system-level debug and root-cause analysis through bringup, characterization, validation and production phase.
9) Working with 3rd party IP and memory vendors

## Description

Engage in definition, design and validation of AWS next generation ML Chips, Cards and server integration. * Participate in the design and execution of all HBM, Memories and Serdes topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. * Work with vendors, understand the settings, write/modify tests, debug and collect data in the fleet * Participate in the code review process, design discussions, team planning, and ticket/metric/COE reviews * Collaborate with architects, design teams, software engineers to deliver the next generation ML chip. * Responsible for IP integration, 2.5D design, bring up, Characterization and validation. * Focus on operational excellence, constructively identifying problems and proposing solutions.