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# Modeling Architect

- **Company:** Neurophos Inc.
- **Location:** San Mateo, CA, United States
- **Experience:** Experienced
- **Salary:** $170,000.0 - $200,000.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Nvidia CUDA, Computer Engineering, Software Debugging, Dynamic Random-Access Memory, Data Flow Control, Python (Programming Language), SystemC, SystemVerilog, Verilog, Network Switches, Pytorch, Large Language Models, Caching, Gpu Programming, Information Technology, Instruction Set Architecture, HuggingFace, Decoding, C++14
- **Published:** September 3, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=178e384f449ce4f2

## About the Role

* BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or a related field.
 * 3+ years of experience in hardware modeling, performance simulation, computer architecture, or related work.
 * Proficiency in Python or modern C++ (C++17 or later). Python-first and C++-first backgrounds are both welcome.
 * Working knowledge of computer architecture and microarchitecture, including pipelines, caches, memory hierarchies, and instruction set architecture (ISA).
 * Ability to turn an LLM, GEMM, or accelerator paper into a workload config using Hugging Face or PyTorch.
 * Strong debugging skills and the habit of writing down what was run, what was assumed, and what the number means.

Preferred Skills

 * MS or PhD in Computer Engineering, Electrical Engineering, or Computer Science.
 * Experience with roofline analysis, limiter analysis, GPU benchmarking, or correlating a model against published numbers.
 * Event-driven, cycle-approximate, or cycle-accurate simulation with SystemC, gem5, SST, or a custom kernel.
 * SystemVerilog, Verilog, Verilator, or RTL co-simulation.
 * Memory and interconnect experience with HBM, DRAM, cache, SRAM, network-on-chip (NoC), AXI, or DMA.
 * Familiarity with CUDA, GPU programming, or PyTorch internals.

## Description

We are seeking a modeling architect for hands-on architecture modeling of the T100 optical inference accelerator, with hardware/software co-design in the loop. You will work alongside senior engineers across two tracks. The first is analytical and system performance: roofline and limiter analyses, architecture performance models, workload setup, and the resulting plots and reports. The second is hardware models: functional, performance, and power models of compute blocks, memory, and hardware/software interfaces built in an event-driven simulator, plus RTL simulation.

We expect real depth in one track and will help you build breadth across both. Most engineers start with a bounded piece, a single workload, a hardware block, or one layer of the model stack, and take on the surrounding area as the models mature., * Bring up inference workloads as they ship, including dense and Mixture of Experts (MoE) transformers, hybrid/SSM models, prefill versus decode, KV cache, expert routing, and quantization, plus retrieval, speech, vision, and recommendation workloads where they map onto the accelerator.

 * Bind Hugging Face and PyTorch workloads to the programming model and run them on the functional model.
 * Co-design tiling, scheduling, the instruction set architecture (ISA), the SRAM and High Bandwidth Memory (HBM) hierarchy, and multi-chip mapping.
 * Build in one or more layers of the modeling stack: roofline and limiter studies; Python energy and latency models; C++ functional models of optical GEMM, SRAM vector processors, dataflow engines, and HBM; cycle-approximate performance and power models; and RTL simulation with Verilator and SystemVerilog.
 * Own the tests, configs, and plots behind a result so anyone can rerun it and see what was assumed.
 * Use coding agents on real multi-file edits, and own the review of the C++ and SystemVerilog they generate.
 * Share results with the architects setting the design, as well as the compiler, runtime, and RTL teams, and carry their questions back into the model stack.