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# EDA Engineer

- **Company:** Mojo Vision
- **Location:** Cupertino, CA, United States
- **Experience:** Expert
- **Salary:** $188,000.0 - $230,000.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Artificial Intelligence, Computer Programming, System Configuration, Electronic Design Automation, Perl (Programming Language), Hardware Description Language, Python (Programming Language), Cadence Virtuoso, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Linux Virtual Server, Scripting, Physical Verification, Physical Design
- **Published:** September 10, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=bd615ecb4062ab03

## About the Role

* BSEE or MSEE, and 10+ years of experience in EDA
 * Tools: Expertise in major tools like Cadence, Synopsys (Virtuoso, Encounter, etc.).
 * Scripting: Proficiency in SKILL, Python, Tcl, Perl for automation.
 * Physical Design: Experience with DRC (Design Rule Check), LVS (Layout Versus Schematic), P&R (Place & Route), and related flows.
 * Circuit Design: Understanding of digital and analog IC design principles.
 * Semiconductor Process: Knowledge of fabrication processes and Device Physics.
 * Programming: Familiarity with SKILL and hardware description languages (e.g., Verilog/VHDL) is often required.
 * Experience in full-chip or block-level physical design.
 * Developing/supporting PDKs (Process Design Kits) and PCELLs.

Valuable Additional Qualifications:

 * Experience with leading and mentoring layout team members

Preferred Skills:

 * Strong interpersonal and problem-solving skills
 * Prior experience bringing communication products to mass production

## Description

* Design Flow Development & Automation: Developing and maintaining specialized software flows for Analog flows, front-end (RTL, simulation), and back-end (synthesis, place and route, timing) design stages.
 * CAD Methodology Improvement: Evaluating and enhancing design methodologies to increase efficiency, such as implementing AI-driven design automation or customizing scripts in SKILL, Python, Tcl, or Perl to streamline repetitive tasks.
 * Tool Configuration and Support: Installing, configuring, and troubleshooting Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, or Siemens-EDA to ensure they meet project-specific requirements.
 * Physical Verification & Sign-off: Managing design rule checks (DRC), layout vs. schematic (LVS) verification, and parasitic extraction to ensure the chip is manufacturable (tape-out ready).
 * PDK and Library Management: Maintaining Process Design Kits (PDKs) and standard cell libraries provided by foundries to ensure accurate simulation and layout.


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