> Markdown version of [/jobs/ext/3324685-asic-diagnostic-silicon-bring-up-engineer](https://www.wearedevelopers.com/jobs/ext/3324685-asic-diagnostic-silicon-bring-up-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# ASIC Diagnostic & Silicon Bring-Up Engineer

- **Company:** Eridu Corporation
- **Location:** United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Automation of Tests, C++ (Programming Language), Configuration Management, Computer Programming, Software Debugging, Emulators, Ethernet, Firmware, Python (Programming Language), PCI Express, AI Infrastructure, Scripting, Application Specific Integrated Circuits, Build Management, Data Pipelines
- **Published:** September 4, 2026
- **Apply:** https://startup.jobs/asic-diagnostic-silicon-bring-up-engineer-eridu-8309001

## About the Role

* Bachelor's with 10+ years or Master's with 5+ years of relevant experience
 * Strong experience in ASIC bring-up / post-silicon validation and hardware-software debug
 * Strong programming skills in Python (mandatory), along with C/C++ and scripting
 * Experience building diagnostic frameworks, automation tools, and test orchestration systems

Preferred Qualifications

 * Experience with SERDES , UCIe / chiplet architectures, or networking ASICs
 * Familiarity with packet processor SDKs and emulation platforms
 * Experience with BER testing tools and SERDES tuning/margining
 * Exposure to CI/regression infrastructure for silicon validation

## Description

We are looking for a Senior ASIC Diagnostics Engineer to drive post-silicon bring-up, debug, and validation of next-generation high-performance ASICs. This role focuses on building diagnostic infrastructure, automation frameworks, and debug tools to validate ASIC functionality across SERDES, high-speed interfaces, and packet processing pipelines., * Develop diagnostics for early silicon validation and debug

 * Lead bring-up of ASIC silicon on characterization and validation platforms
 * Validate power, reset, and clocking sequences, along with register access and initialization flows
 * Design and build Python-based diagnostic frameworks for register access, configuration management, and test orchestration; convert debug procedures into automated test flows
 * Develop diagnostics for SERDES links (training, BER, eye margining), Ethernet, PCIe, and UCIe / chiplet interfaces
 * Use SDKs and internal tools to generate traffic, verify data path correctness, and validate counters and statistics
 * Integrate and correlate behavior across RTL verification, emulation platforms, and silicon; develop correlation tools and methodologies
 * Perform deep debug across ASIC logic, interfaces, and firmware interactions; isolate functional mismatches, timing/clocking issues, and protocol failures
 * Develop automated diagnostics and integrate into regression frameworks and continuous validation pipelines