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# Lead/Principal DFT Engineer

- **Company:** Fractile
- **Location:** Bristol, UK
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Multiprocessing, Physical Design
- **Published:** September 5, 2026
- **Apply:** https://startup.jobs/lead-principal-dft-engineer-fractile-8291397

## About the Role

* Strong experience in DFT for complex ASIC/SoC designs (typically 10+ years)
 * Proven ownership of DFT architecture on at least one large tapeout
 * Deep expertise in scan, compression, ATPG, and MBIST
 * Experience with industry tools (Synopsys or Tessent)
 * Strong understanding of clocking, resets, power domains, and physical constraints
 * Experience with silicon bring-up, debug, and yield ramp

Profile

 * Comfortable owning ambiguous, high-impact problems
 * Balances architectural thinking with hands-on execution
 * Sets direction while staying close to implementation details

## Description

* Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan)
 * Set DFT strategy, methodology, flow and signoff criteria
 * Drive integration of DFT tools and flows into the overall EDA environment
 * Define hierarchical DFT approach for multi-core designs and large memory systems
 * Define scan architecture, compression strategy, and ATPG approach
 * Define memory test and repair strategy for large embedded RAM
 * Establish power-aware and at-speed test strategies
 * Work closely with RTL and physical design to ensure clean DFT integration and timing closure
 * Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp
 * Mentor and guide DFT engineers


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