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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Digital ASIC Design Engineer - **Company:** Empfehlungsbund And Mintsax - **Location:** Dresden, Germany - **Experience:** Expert - **Salary:** €68,000.0 - €85,000.0 - **Contract:** Internship / Graduate position - **Skills:** 4G (Telecommunication), Systems Engineering, Bluetooth, Computer Engineering, Logic Synthesis of Circuits, Digital Technology, Electronic Design Automation, Perl (Programming Language), Emulators, Firmware, Formal Verification, Field-Programmable Gate Array (FPGA), Python (Programming Language), Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Verilog, Wi-Fi Technology, Scripting, Application Specific Integrated Circuits, 5G NR, State Machines, Information Technology, Code Inspection - **Published:** September 15, 2026 - **Apply:** https://www.mintsax.de/jobs/306427/digital-asic-design-engineer-m-strich-f-strich-x-in-dresden#apply_form ## About the Role * A bachelor's or master's degree in electrical engineering, microelectronics, telecommunications engineering, computer science, computer engineering, or a comparable qualification. * Several years of practical experience in digital design for ASICs, SoCs, FPGAs, or comparable complex embedded systems; typically, you have at least five years of relevant professional experience outside of your studies and internships. * Solid practical experience in RTL design using Verilog and/or SystemVerilog. * A solid understanding of digital circuit design, synchronous logic, finite-state machines, data paths, registers, memory, and digital interfaces. * Experience with timing, clocking, reset strategies, and the fundamental requirements for synthesis and physical implementation. * You can translate technical requirements into clearly structured, robust, and verifiable RTL implementations. * Experience with digital interfaces, register definitions, and the integration of hardware/software interfaces. * Ability to evaluate design decisions regarding performance, area, power consumption, timing, complexity, and robustness. * Experience analyzing and resolving RTL, integration, timing, and verification issues. * A structured, analytical, and solution-oriented approach to work, as well as a high degree of personal responsibility. * Good written and spoken English skills for working in an international team. Nice-to-have: * Experience with + complex SoC/ASIC designs, particularly those with multiple clock domains and mixed-signal or RF interfaces. + DECT NR+, DECT-2020, 4G/5G, Wi-Fi, Bluetooth, or comparable communication systems. + EDA tools for RTL simulation, linting, CDC/RDC analysis, synthesis, and timing analysis. + Tcl, Python, Perl, or comparable scripting languages for automating design and analysis workflows. + Low-power design, clock gating, power intent, or UPF. + FPGA prototyping, emulation, ASIC tape-out, or silicon bring-up. + DFT, scan, ATPG, or manufacturing test requirements. * Knowledge of SystemVerilog, assertions, simulation-based verification, formal verification, or UVM. Good knowledge of hardware/software interfaces, register maps, firmware requirements, and driver concepts. * Experience with safety-critical, reliability-critical, or highly energy-efficient embedded systems. * Experience in establishing and refining coding guidelines, design reviews, and reproducible development processes. * Experience in a startup or scale-up environment, as well as a passion for pragmatic decision-making and short development cycles. ## Description We are looking for an experienced professional to join us as a Senior Digital ASIC Design Engineer, who will strengthen our digital design team and work with us on the development of modern ASIC and SoC systems. In this role, you will develop digital ASIC/SoC components from specification through RTL implementation and verification to handoff to synthesis and physical implementation. If you independently design complex digital systems, translate requirements into robust and verifiable RTL architectures, and enjoy working at the intersection of SoC architecture, digital design, verification, firmware, analog/RF, and physical implementation, then you've come to the right place., * Developing digital ASIC/SoC components from specification through RTL design and verification to handoff to synthesis and physical implementation. * Implementation of digital functions in Verilog and SystemVerilog, taking into account performance, chip area, power consumption, latency, and timing. * Developing data paths, control logic, state machines, registers, memories, interfaces, and digital subsystems. * Translating system and block requirements into clearly structured, robust, and verifiable RTL architectures. * Creation and maintenance of design specifications, register definitions, and interface and integration documentation. * Defining and coordinating interfaces between digital blocks as well as with analog, RF, and firmware components. * Supporting the integration of digital blocks into complex SoC and mixed-signal environments. * Close collaboration with SoC Architecture, Design Verification, Synthesis & Physical Implementation, Firmware, System Engineering, and Analog/RF Design. * Analysis and resolution of design, integration, timing, and verification issues across teams and domains. * Support for linting, clock-domain crossing, reset-domain crossing, and formal checks. * Support for synthesis, as well as the preparation and handoff of RTL, constraints, and technical documents to Synthesis & Physical Implementation. * Supporting the development process from architecture and RTL implementation through tape-out, silicon bring-up, and product release. * Creation and maintenance of design, integration, and verification documentation. * Early identification of technical risks, as well as coordination and implementation of appropriate countermeasures. * Contributing to the further development of design methods, coding guidelines, review practices, and development processes in a growing deep-tech company. ## Related Videos - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Agent Smith Gets Hardware: Autonomous IoT Hacking From Debug Port to Cloud API](https://www.wearedevelopers.com/videos/100258-agent-smith-gets-hardware-autonomous-iot-hacking-from-debug-port-to-cloud-api) - [Unlocking the potential of Digital & IT at Vodafone](https://www.wearedevelopers.com/videos/602-unlocking-the-potential-of-digital-it-at-vodafone) - [My ongoing quest to code in VR](https://www.wearedevelopers.com/videos/2080-my-ongoing-quest-to-code-in-vr) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) ## Related Articles - [The Most Popular IT Jobs on the Market](https://www.wearedevelopers.com/magazine/376-the-most-popular-it-jobs-on-the-market) - [Austria – the most livable place for software developers?](https://www.wearedevelopers.com/magazine/20-austria-the-most-livable-place-for-software-developers) - [Top-Paying Tech Jobs (with Salaries)](https://www.wearedevelopers.com/magazine/372-top-paying-tech-jobs-with-salaries) - [Software Developer Salary in Austria [2023]](https://www.wearedevelopers.com/magazine/213-software-developer-salary-in-austria-2023) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [System change: restart as developer?](https://www.wearedevelopers.com/magazine/39-system-change-restart-as-developer)