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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Synthesis and Physical Implementation Engineer Digital Design - **Company:** Empfehlungsbund And Mintsax - **Location:** Dresden, Germany - **Experience:** Expert - **Salary:** €60,000.0 - €75,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Software Debugging, Electronic Design Automation, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Python (Programming Language), Routing, Regression Testing, Signal Integrity, Static Timing Analysis, Tcl (Programming Language), Linux Virtual Server, Scripting, Application Specific Integrated Circuits, Backend, Information Technology, Power Analysis (Cryptography), Physical Verification, Physical Design, Software Version Control - **Published:** September 14, 2026 - **Apply:** https://www.mintsax.de/jobs/306325/digital-design-synthesis-and-physical-implementation-engineer-m-slash-f-slash-x-in-dresden#apply_form ## About the Role * A bachelor's or master's degree in electrical engineering, microelectronics, computer engineering, computer science, or a comparable qualification. * Senior-level, independent professional experience in ASIC backend, synthesis, physical implementation, digital backend, or a closely related semiconductor design field; as a guideline, you have at least seven years of relevant experience. * Practical experience with ASIC synthesis and physical implementation, as well as a solid understanding of the RTL-to-gate and RTL-to-layout flows. * Strong knowledge of synthesis, timing constraints, static timing analysis, and design optimization. * A solid understanding of clocking, reset behavior, timing paths, setup and hold requirements, and timing closure. * Experience with scripting for design automation and analysis, for example, using Tcl, Python, Perl, or similar languages. * You can analyze implementation reports in a structured manner and identify issues related to timing, area, power, congestion, and constraints. * Experience with floorplanning, placement, clock-tree synthesis, routing, extraction, and physical sign-off. * Experience with leading EDA tools from Synopsys, Cadence, Siemens EDA, or comparable tool environments. * A structured, analytical, and solution-oriented approach to work, as well as a high degree of personal responsibility. * Very good English skills at a minimum B2 level; knowledge of German is a plus. * Nice-to-have: + Experience with advanced timing constraints, clock-domain crossings, multi-cycle paths, and false-path definitions. + Knowledge of low-power design, power intent, UPF, multi-voltage domains, or power analysis. + Experience with DRC, LVS, antenna checks, design rule debugging, or other physical verification activities. + Experience with mixed-signal SoCs as well as the implementation requirements for analog/RF interfaces and hard macros. + Experience with ASIC tape-out, foundry handover, PDKs, technology libraries, or silicon bring-up. + Experience with FPGA implementation or prototyping. + Experience with automated regression testing, CI environments, version control, and reproducible implementation flows. + Knowledge of DFT, scan insertion, ATPG, test constraints, or manufacturing test requirements. + Experience in establishing or improving synthesis and physical implementation processes in a startup or scale-up environment. ## Description * Developing and maintaining the digital implementation flow from RTL through synthesis and physical implementation to physical realization. * Performing and analyzing logic synthesis, including constraint setup, technology mapping, and netlist generation. * Creating, maintaining, and optimizing timing, clock, input/output, and design constraints. * Supporting floorplanning, placement, clock-tree synthesis, routing, and design optimization. * Analyzing and improving timing, area, power, and congestion results. * Identifying and resolving implementation issues in close collaboration with the RTL, SoC architecture, design verification, and physical design teams. * Support for static timing analyses, signal integrity analyses, and other relevant implementation checks. * Preparing and documenting handover data for physical verification, sign-off, and manufacturing-related activities. * Coordinating implementation requirements and interfaces with the Analog/RF, Mixed-Signal, and Layout teams. * Support for design rule checks, layout-versus-schematic checks, and other physical sign-off activities, as required by the respective project. * Developing and maintaining scripts and automations for synthesis, implementation, analysis, and regression flows. * Documentation of flow configurations, assumptions, constraints, results, open issues, and implementation risks. * Support for pre-tape-out readiness reviews and the preparation of implementation deliverables. * Building and further developing expertise, processes, and tooling related to synthesis and physical implementation. * Continuous improvement of implementation flows, reusable scripts, reporting structures, and handover processes. ## Related Videos - [Creating a routing app with Google Maps API from scratch](https://www.wearedevelopers.com/videos/831-creating-a-routing-app-with-google-maps-api-from-scratch) - [Developing the Backend with Stefan Lingler, CTO at Shpock](https://www.wearedevelopers.com/videos/100360-developing-the-backend-with-stefan-lingler-cto-at-shpock) - [JavaScript? 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