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# Senior Memory System Engineer

- **Company:** NVIDIA Corporation
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Salary:** $184,000.0 - $287,500.0
- **Contract:** Permanent contract
- **Skills:** Systems Engineering, Software Documentation, Computer Engineering, Software Debugging, Microprocessors, Dynamic Random-Access Memory, Firmware, Python (Programming Language), Subsystems, Systems Architecture, Virtual Memory, Application Specific Integrated Circuits, Pcb Layout
- **Published:** September 22, 2026
- **Apply:** https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Memory-System-Engineer_JR2005335

## About the Role

* Bachelor's degree or master's degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience)
 * 10 years of proven track record in DRAM design, module design, or memory sub system design.
 * Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM.
 * Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY.
 * Experience in the design, bring-up and validation for memory failure analysis
 * Experience with Python, C/C++ for development and memory workload analysis.
 * Strong user documentation and interpersonal skills

## Description

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs.

What You Will Be Doing:

 * Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems.
 * Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers.
 * Define Memory module, Package, and PCB layouts appropriate to the system workloads
 * Debug and bring up memory evaluation / validation and failure issues on memory technology.
 * Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology.