> Markdown version of [/jobs/ext/3360067-working-student-r-d-digital-memory-subsystem-iv](https://www.wearedevelopers.com/jobs/ext/3360067-working-student-r-d-digital-memory-subsystem-iv). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Working Student - R&D Digital Memory Subsystem iv) - **Company:** Infineon Technologies AG - **Location:** München, Germany - **Contract:** Temporary contract - **Skills:** Bash Shell, Databases, Database Schema, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Machine Learning, NumPy, Shell Script, Subsystems, SystemVerilog, Tcl (Programming Language), VHSIC Hardware Description Language (VHDL), Git, Pandas, Information Technology - **Published:** September 5, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=560382839d1c2255 ## About the Role * Study field: A Bachelor's degree in Electrical Engineering, Information Technology or similar studies with focus on electronics * Knowledge: Knowledge of VHDL, System Verilog including experience on CPU and memory designs together with functional and corner case verification * Skills: + Python for automation/data (pandas/numpy), Bash/Tcl; + Git, Linux/Unix RTL/VHDL/System Verilog and timing/SDC basics + Logic synthesis/reporting; handling netlists/Liberty + Basic knowledge of directed verification + Nice to have: MBIST/DFT fundamentals Familiarity with Linux/Unix environments and shell scripting * Way of working: Analytical, organized, and curious person. Methodical debugging, proactive and collaborative colleague * Language skills: Fluent in English. Please attach the following documents to your application: * CV in English * Certificate of enrollment at university * Latest grades transcript (not older than 6 months) * High school report ## Description * Focus on the future: Understand and enhanced memory sub system automation environment with EDA tools * Take responsibility: Integrate MBIST generation into the subsystem build (wrappers, controllers, constraints, sanity checks) * Reliable work: Execute synthesis across diverse configurations; standardize and store KPIs (area, Fmax/slack, power if available, EDA runtime/peak memory, MBIST overhead) * Keep up to date: Provide support in RTL design for memory sub system IPs Build robust parsers and data schemas; track provenance (tool versions, seeds, constraints * Identify needs: Work with the existing structured results database to surface build and evaluation data Train ML models to identify Pareto-optimal configurations and recommend next experiments