> Markdown version of [/jobs/ext/3371540-front-end-asic-digital-design-sr-staff-engineer-18423](https://www.wearedevelopers.com/jobs/ext/3371540-front-end-asic-digital-design-sr-staff-engineer-18423). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Front-End ASIC Digital Design, Sr. Staff Engineer -18423 - **Company:** Synopsys - **Location:** Austin, TX, United States - **Experience:** Expert - **Salary:** $138,000.0 - $208,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Microarchitecture, Linux, Logic Synthesis of Circuits, Perl (Programming Language), Ethernet, Python (Programming Language), PCI Express, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Verilog, Application Specific Integrated Circuits, Front End Software Development, Physical Design - **Published:** September 22, 2026 - **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/18409893?backUrl=%2Fcareer%2F18409893%2FFront-End-Asic-Digital-Design-Sr-Staff-Engineer-18423-Texas-Austin ## About the Role * BS/MS in Electrical/Computer Engineering or a related field, with 8+ years of experience in ASIC design and STA sign-off. * Demonstrated experience with front-end sign-off flows: STA (PrimeTime), lint (SpyGlass), and CDC/RDC. * Strong proficiency in SystemVerilog/Verilog RTL coding for synthesis. * Solid understanding of synthesis (Design Compiler / Fusion Compiler) and QoR analysis. * Experience with low-power design techniques: clock gating, power gating, multi-Vt, UPF. * Working knowledge of SDC constraint development and timing closure methodology. * Proficiency in scripting: TCL, Python, Perl, and Linux/UNIX environments. * Command of digital design fundamentals: FSMs, arbitration, clock domain crossing, memory interfaces, and standard protocols (AMBA AXI/AHB/APB). * High-speed interface IP integration experience (PCIe, DDR/LPDDR, Ethernet, USB, MIPI)., * Curious and improvement-minded: You identify an inefficient workflow, which you then automate and turn it into a reusable capability for everyone. * Accountable and proactive:You are hands-on and take the lead and responsibility for driving issues to a closure. * A clear communicator: Your specifications, review feedback, and sign-off documentation provide clear guidance for stakeholders. * Highly detail-oriented:You follow quality and sign-off checklists rigorously and prioritize finding issues early in the process than at a later stage. #LI-NK4 ## Description We are seeking a Front-End ASIC Design Engineer with hands-on experience taking RTL from specification through design sign-off. You will own RTL blocks for high-performance SoCs, drive synthesis and timing closure quality at the front-end boundary, and ensure designs are clean against lint, CDC/RDC, timing, and power sign-off criteria before hand-off to physical design. What You'll Be Doing: * Drive front-end sign-off: static timing analysis (STA), lint, CDC/RDC, synthesis, and power efficient design. * Translate architectural specifications and micro-architecture documents into synthesizable RTL (SystemVerilog/Verilog) for blocks and subsystems. * Own timing constraint (SDC) development and review; support full-chip timing closure. * Perform synthesis, QoR analysis, and iterative RTL optimization for area, timing, congestion, and power. * Apply formal property verification (VC Formal) and assertion-based design (SVA) to validate block behavior. * Run power estimation and analysis (PrimePower) and feed findings back into RTL optimization. * Contribute to methodology improvement, scripting, and regression automation. ## Related Videos - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Docker exec without Docker](https://www.wearedevelopers.com/videos/1094-docker-exec-without-docker) ## Related Articles - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data) - [How Much FAANG Companies Actually Pay Software Engineers in 2025](https://www.wearedevelopers.com/magazine/230-how-much-faang-companies-actually-pay-software-engineers-in-2025)