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# Principal FPGA Emulation Engineer

- **Company:** Renesas Electronics America Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Board Bringup, C++ (Programming Language), Computer Engineering, Software Debugging, Emulators, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Hardware-In-The-Loop Simulation, Python (Programming Language), MATLAB, PCI Express, Signal Integrity, Simulink, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Model-Driven Development, Application Specific Integrated Circuits, Physical Design
- **Published:** September 13, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=390ec25a97e7d436

## About the Role

* Extensive FPGA design and implementation experience (typically 10+ years), including a track record of FPGA prototyping or emulation of ASIC/SoC designs.
 * Expert-level RTL design in SystemVerilog and/or VHDL, with deep familiarity working from ASIC-style RTL.
 * Deep understanding of FPGA internal architecture and primitives - DSP/multiplier slices, block and distributed RAM, carry chains, and clocking - and a proven ability to map designs onto these resources to fit large ASIC RTL and reach real-time emulation performance (memory/SRAM macro mapping, DSP inference, clock-enable conversion, control-set and fanout management).
 * Hands-on experience adapting ASIC RTL for FPGA: clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling.
 * Strong command of the full FPGA implementation flow - synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) - on large Xilinx and/or Intel (Altera) devices, using Vivado and/or Quartus.
 * Hardware bring-up and debug experience: in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug.
 * Proficiency scripting for automation (TCL, Python).
 * Demonstrated technical leadership - mentoring, reviews, and driving cross-team technical decisions.
 * BS or MS in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience)., * Real-time, hardware-in-the-loop emulation and modeling of analog/mixed-signal and power stages (ADC/DAC/PWM interfaces, plant/converter models).
 * Understanding of digital power-conversion control and mixed-signal systems - converter topologies, control loops, PWM/PFM, and magnetics - to build faithful models and validate power-control architectures.
 * FPGA DSP implementation and real-time emulation of DSP datapaths: FIR/IIR/CIC filters, interpolation/decimation, FFT, FEC, including high-throughput techniques such as folding/unfolding.
 * Experience with commercial FPGA prototyping platforms such as Synopsys HAPS, Cadence Protium, or Siemens Veloce.
 * Model-based design with Simulink and/or Xilinx System Generator.
 * High-speed interface experience: JESD204B, PCIe, 1G/10G Ethernet, Aurora.
 * ASIC design or tape-out exposure, including DFT/scan considerations in emulation.
 * Ability to architect and build a custom in-house FPGA prototyping platform - board architecture, high-speed PCB design, signal integrity, and bring-up - a plus as we may develop our own hardware in the future.
 * Embedded/microcontroller and firmware co-development experience (C/assembly); MATLAB, C/C++.

## Description

* Partner closely with silicon RTL and DSP architects to bring ASIC designs up on FPGA - advising on FPGA-ability and turning architectural intent into a working, real-time emulation platform.
 * Adapt ASIC RTL for FPGA emulation while preserving functional equivalence to the golden design - handling clock-gating conversion, memory/SRAM macro mapping, reset and initialization schemes, tri-state/bus conversion, and stubbing or modeling of analog/mixed-signal blocks.
 * Map designs onto the FPGA fabric to fit and to hit emulation speed - steering resource inference (DSP/multiplier slices, block vs. distributed memory), clocking, and pipelining so the design achieves the real-time performance the validation requires.
 * Build the real-time environment around the digital core: model or interface to the analog and power stages (ADC/DAC/PWM, gate drivers, plant/converter models), including hardware-in-the-loop with real or emulated power hardware where needed.
 * Develop deep pre-silicon debug and visibility - logic analysis, long-run waveform capture, triggering, and assertions - and enable firmware/software co-development ahead of silicon.
 * Define and continuously improve the emulation methodology, RTL/FPGA-ability guidelines, flows, and automation (TCL/Python).
 * Provide technical leadership: mentor engineers, lead reviews, and drive emulation and tooling decisions across the silicon and systems teams.