> Markdown version of [/jobs/ext/338404-digital-design-verification-engineer](https://www.wearedevelopers.com/jobs/ext/338404-digital-design-verification-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Digital Design Verification Engineer - **Company:** OLIX - **Location:** Bristol, UK - **Experience:** Expert - **Salary:** £36,000.0 - £125,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Software Debugging, Logic Synthesis of Circuits, Ethernet, Firmware, Formal Verification, Field-Programmable Gate Array (FPGA), Python (Programming Language), MATLAB, NumPy, Open Source Technology, PCI Express, SystemVerilog, Real Time Data, Code Inspection, Hardware Acceleration - **Published:** June 10, 2026 - **Apply:** https://uk.indeed.com/viewjob?jk=7f3e3d57ddb71ac3 ## About the Role Do you have experience in SystemVerilog?, * 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs * Ownership of verification for at least one complex block or subsystem processing continuous real-time data streams * Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (e.g. UVM. CocoTB) * Proven experience verifying designs operating in GHz-class clock domains, including CDC/RDC analysis * Familiarity with industry-standard EDA flows: RTL simulation, formal verification, linting, CDC/RDC, STA, power-intent (UPF/CPF), and gate-level simulation * Experience verifying high-speed IP such as SerDes, DDR/HBM, PCIe, Ethernet, or similar interfaces * Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis, and test-vector generation * Solid grounding in digital design principles, computer architecture, DSP fundamentals, and semiconductor basics * Clear communicator who collaborates effectively across disciplines and is comfortable operating in a fast-moving, evolving environment Nice to have * Tape-out experience at 22 nm or below * Deep hands-on experience with formal verification methodologies, including property decomposition, and coverage-driven formal on tools such as Jasper * Exposure to coherent optical links or photonic-electronic co-design * Familiarity with AI/ML workloads, systolic arrays, or tensor-processing architectures * Expertise in arithmetic pipeline verification * Expertise in processor and ISA verification * Contributions to open-source RTL, verification frameworks, or FPGA platforms ## Description We are seeking highly skilled and motivated Senior / Staff Digital Verification Engineers with a strong background in CMOS digital design and verification to take ownership of the functional correctness of high-speed, real-time data-processing silicon-from early algorithm modelling through verified RTL, sign-off, and silicon bring-up. You will join a multidisciplinary group creating groundbreaking hardware where digital, optical, and mixed-signal domains intersect. The ideal candidate brings deep expertise in digital verification methodologies, a solid understanding of hardware architecture, and a passion for building provably correct, high-performance systems that underpin breakthrough AI hardware., * Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, deep pipelining, and robust hand-shaking in advanced CMOS nodes * Develop and maintain comprehensive verification environments using SystemVerilog/UVM, including constrained-random testing, coverage closure, and regression automation * Define and implement assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance * Apply formal verification techniques (property checking, assertions, equivalence checking) to complement simulation-based verification and accelerate bug discovery * Model and validate algorithms using MATLAB/Simulink or Python, ensuring functional equivalence from algorithmic models through RTL and gate-level sign-off * Support FPGA prototyping and silicon bring-up by developing targeted testcases, debug strategies, and post-silicon validation plans * Collaborate closely with digital design, optical-hardware, mixed-signal, and software teams to ensure correct integration across clock domains, interfaces, and firmware abstractions * Analyse verification results to identify root causes, drive design fixes, and improve verification efficiency and reuse * Contribute to verification methodology development, documentation, and design/verification reviews; mentor junior engineers where appropriate ## Related Videos - [Leveraging Large Language Models for Legacy Code Translation: Challenges and Solutions](https://www.wearedevelopers.com/videos/1157-leveraging-large-language-models-for-legacy-code-translation-challenges-and-solutions) - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [Vectorize all the things! Using linear algebra and NumPy to make your Python code lightning fast.](https://www.wearedevelopers.com/videos/562-vectorize-all-the-things-using-linear-algebra-and-numpy-to-make-your-python-code-lightning-fast) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) ## Related Articles - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Dev Digest 230: Secure Agent Sandboxes, $100m OSS & Tricking Claude](https://www.wearedevelopers.com/magazine/744-dev-digest-230-secure-agent-sandboxes-100m-oss-tricking-claude) - [Dev Digest 188: CfP time, the risks of NPM and IKEA algorithms](https://www.wearedevelopers.com/magazine/635-dev-digest-188-cfp-time-the-risks-of-npm-and-ikea-algorithms) - [Dev Digest 150 - The shift to AI generated code, fingerprinting and OKRs vs. doing your job](https://www.wearedevelopers.com/magazine/533-dev-digest-150-the-shift-to-ai-generated-code-fingerprinting-and-okrs-vs-doing-your-job) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 131 - AI'm not sure about OSS](https://www.wearedevelopers.com/magazine/472-dev-digest-131-ai-m-not-sure-about-oss)