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# Hardware Design Engineer 2

- **Company:** CYNET SYSTEMS INC.
- **Location:** United States
- **Salary:** $126,277.0 - $135,200.0
- **Contract:** Permanent contract
- **Skills:** Unit Testing, C++ (Programming Language), Computer Engineering, Software Debugging, Digital Architecture, Logic Synthesis of Circuits, Perl (Programming Language), Firmware, Python (Programming Language), SystemVerilog, Tcl (Programming Language), Verilog, Scripting
- **Published:** September 11, 2026
- **Apply:** https://www.thejobnetwork.com/job/53157954-9cfc-44e4-8b54-f3e798f896a6/hardware-design-engineer-

## About the Role

* Digital design engineering experience.
 * Experienced with Verilog, System Verilog, C, and C++.
 * Excellent knowledge of Verilog, System Verilog and a scripting language.
 * Knowledge of clocking architectures, synchronization, and CDC methodology.
 * Experience with synthesis and timing closure.
 * Strong understanding of computer organization/architecture.
 * Bachelors or Masters degree in Computer Engineering or Electrical Engineering., * Experience with Python, Perl, and TCL.
 * SERDES, DDR, Memory Controller, or MAC Design experience.
 * Mixed signal RTL and Low power design experience.
 * Exposure to leadership or mentorship.

Skills:

 * RTL Design.
 * Verilog.
 * System Verilog.
 * C.
 * C++.
 * Python.
 * Perl.
 * TCL.
 * Timing Synthesis.
 * LPDDR.
 * DDR IP.
 * Memory PHY.
 * Digital Architecture.

Qualification And Education:

 * Strong analytical and problem-solving skills.
 * Strong verbal and written communication skills.
 * Ability to communicate effectively with stakeholders.
 * Team player with experience collaborating across different sites and timezones.

## Description

* Perform RTL design for memory I/O PHY.
 * Develop Digital Architecture from pathfinding, coding, and verification to physical implementation.
 * Execute PHY link layer design, implementation, and verification with Analog and System architects.
 * Perform PHY Analog/Digital co-design.
 * Conduct digital design and RTL coding.
 * Manage Timing Synthesis and drive physical implementation.
 * Collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified.
 * Estimate time required for new feature tests and required changes to the test environment.
 * Build unit tests.
 * Debug design failures to determine root cause and work with DV and firmware engineers to resolve defects.