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# Senior FPGA Engineer

- **Company:** Randstad
- **Location:** North Reading, MA, United States
- **Experience:** Expert
- **Salary:** $190,000.0 - $200,000.0
- **Contract:** Permanent contract
- **Skills:** Systems Engineering, ARM Architecture, Bioinformatics, C++ (Programming Language), Data Transmissions, Software Debugging, Firmware, Field-Programmable Gate Array (FPGA), Python (Programming Language), PCI Express, Signal Integrity, Static Timing Analysis, System Testing, SystemVerilog, Systems Integration, Verilog, Vivado, Fpga Hardware, Physical Design
- **Published:** September 25, 2026
- **Apply:** https://www.randstadusa.com/jobs/141/1111023/senior-fpga-engineer_north-reading/

## About the Role

* Professional Engineer
 * Python
 * Project Management
 * Robotics
 * Engineering
 * C
*

## Description

job summary:
Seeking an FPGA Engineer for a high growth test equipment development and manufacturing client in the North Reading, MA area.

The FPGA Engineer would be responsible for you will design, implement, and verify high-performance FPGA architectures that power Teradyne's next-generation Automated Test Equipment. You will collaborate with cross-functional teams spanning hardware, software, and systems engineering to solve complex signal integrity, processing, and high-speed data transmission challenges.

Full W-2 benefits offered! Great compensation package including bonuses and stock options! Paid relocation!

Apply now!
location: NORTH READING, Massachusetts
job type: Permanent
salary: $190,000 - 200,000 per year
work hours: 8am to 4pm
education: Bachelors

responsibilities:

 * RTL Design & Architecture: Write clean, maintainable SystemVerilog/Verilog for high-density, high-speed FPGAs (AMD/Xilinx Vivado, Intel/Altera Quartus).
 * System Integration: Integrate embedded processors (e.g., MicroBlaze, ARM Cortex, PCIe controllers) and high-speed serial transceivers (Multi-Gigabit Transceivers).
 * Timing Closure: Perform complex synthesis, place-and-route, Static Timing Analysis (STA), and achieve timing closure on ultra-high-frequency designs.
 * Verification & Debug: Design verification testbenches in SystemVerilog/UVM and perform lab debugging using logic analyzers, high-speed oscilloscopes, and internal FPGA debug tools (e.g., ILA, SignalTap).
 * Cross-Functional Collaboration: Partner with board-level hardware engineers, firmware developers, and software teams to define hardware/software boundary interfaces and ensure system validation.

qualifications:

 * Experience level: Experienced
 * Minimum 10 years of experience
 * Education: Bachelors (required)

skills:

 * Professional Engineer
 * Python
 * Project Management
 * Robotics
 * Engineering
 * C
 * C++
Equal Opportunity Employer: Race, Color, Religion, Sex, Sexual Orientation, Gender Identity, National Origin, Age, Genetic Information, Disability, Protected Veteran Status, or any other legally protected group status.
At Randstad, we welcome people of all abilities and want to ensure that our hiring and interview process meets the needs of all applicants. If you require a reasonable accommodation to make your application or interview experience a great one, please contact HRsupport@randstadusa.com.
Pay offered to a successful candidate will be based on several factors including the candidate's education, work experience, work location, specific job duties, certifications, etc. In addition, Randstad offers a comprehensive benefits package, including: medical, prescription, dental, vision, AD&D, and life insurance offerings, short-term disability, and a 401K plan (all benefits are based on eligibility).
This posting is open for thirty (30) days.
It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.
,

 + RTL Design & Architecture: Write clean, maintainable SystemVerilog/Verilog for high-density, high-speed FPGAs (AMD/Xilinx Vivado, Intel/Altera Quartus).
 + System Integration: Integrate embedded processors (e.g., MicroBlaze, ARM Cortex, PCIe controllers) and high-speed serial transceivers (Multi-Gigabit Transceivers).
 + Timing Closure: Perform complex synthesis, place-and-route, Static Timing Analysis (STA), and achieve timing closure on ultra-high-frequency designs.
 + Verification & Debug: Design verification testbenches in SystemVerilog/UVM and perform lab debugging using logic analyzers, high-speed oscilloscopes, and internal FPGA debug tools (e.g., ILA, SignalTap).
 + Cross-Functional Collaboration: Partner with board-level hardware engineers, firmware developers, and software teams to define hardware/software boundary interfaces and ensure system validation.


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