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# SerDes Characterization Lead, Google Cloud

- **Company:** Google LLC
- **Location:** Sunnyvale, CA, United States
- **Experience:** Expert
- **Salary:** $236,000.0 - $329,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Data Centers, System Testing, Strategies of Testing, IEEE 802.3, Google Cloud, Application Specific Integrated Circuits
- **Published:** September 17, 2026
- **Apply:** https://dejobs.org/x/x/B6F4F28E01CC4181BDA2148C177678E5/job/

## About the Role

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain., * Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.

 * 8 years of experience in high-speed SerDes characterization, silicon and system validation, or electrical physical layer (PHY) design.
 * 5 years of experience in technical leadership driving silicon or hardware characterization programs.
 * Experience participating in or contributing to industry standards bodies (e.g., IEEE, OIF, PCI-SIG, or similar)., * PhD in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
 * Experience architecting automated, high throughput characterization laboratories and test methodologies.
 * Experience in cross-functional and external leadership, establishing relationships across test and measurement vendors, PHY IP suppliers, and standard committees.
 * Subject matter expertise in electrical/optical interconnects, DSP-based SerDes architectures, and advanced channel modeling.
 * Experience in technical vision, and executive communication skills.

## Description

* Serve as the technical lead and owner for high-speed Serializer/Deserializer (SerDes) IP, silicon, and system characterization across next-generation data center and AI/ML accelerator platforms.
 * Define comprehensive SerDes characterization strategies, test methodologies, equipment procurement, and lab automation infrastructure from early silicon bring-up to production readiness.
 * Represent the organization in industry standard bodies (e.g., IEEE 802.3, OIF-CEI) and drive the adoption of emerging electrical and optical interconnect technologies.
 * Partner cross-functionally with Silicon Architecture, ASIC Design, Signal/Power Integrity, System hardware, and Packaging teams to correlate lab measurements with simulations and influence future architecture. Interface with external silicon vendors, IP providers, and test equipment manufacturers to drive ecosystem roadmaps aligned with future infrastructure requirements.
 * Drive next generation interconnect technology pathfinding, vendor engagement, and prototyping efforts. Mentor, guide, and technically lead a team of SerDes characterization engineers.


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