> Markdown version of [/jobs/ext/3424787-senior-digital-mixed-signal-ic-design-or-verification-engineer](https://www.wearedevelopers.com/jobs/ext/3424787-senior-digital-mixed-signal-ic-design-or-verification-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Digital / Mixed-Signal IC Design or Verification Engineer - **Company:** Broadcom - **Location:** Mendota Heights, MN, United States - **Experience:** Expert - **Salary:** $109,700.0 - $175,500.0 - **Contract:** Permanent contract - **Skills:** Analog Electronics, Boolean Algebra, Code Coverage, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Perl (Programming Language), Formal Verification, Python (Programming Language), Oracle Virtual Machine, Broadcom, Software Requirements Analysis, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, Reliability of Systems, Data Management, Physical Design - **Published:** September 11, 2026 - **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-Mendota-Heights-Northland/Senior-Digital---Mixed-Signal-IC-Design-or-Verification-Engineer_R026970-1 ## About the Role * Education/Experience: Bachelors in Engineering and 8+ years of related experience; or Masters degree in Engineering and 6+ years of related experience * Communication: Excellent spoken and written communication skills, and the proven ability to coordinate technical problem-solving across global teams. * Analytical: Proven ability to apply advanced math and physics to solve complex engineering problems. * Bonus: An understanding of silicon process technologies (CMOS and Bipolar) and device physics is a strong plus. Expertise across both design and verification domains is highly desired. Specialized Skills (Design Focus): * Strong hands-on experience with ASIC EDA tools used in synthesis, simulation, static timing analysis, formal verification, and place & route. * Deep familiarity with Verilog/VHDL RTL coding and logic design. Specialized Skills (Verification Focus): * Deep expertise in coverage-driven verification processes and frameworks (UVM/OVM). * Strong understanding of event-driven simulator-based modeling techniques and how digital logic interacts with analog boundaries. * Hands-on experience with SystemVerilog Assertions (SVA) and behavioral modeling of analog circuits. * Proficiency in scripting (Python, Perl, TCL, etc.) to automate verification workflows, manage regressions, and streamline simulation infrastructure. * ## Description We are looking for a Senior Digital IC Design or Mixed-Signal Verification Engineer to act as a methodology leader and key technical bridge for our worldwide engineering organization. This unique opportunity allows you to drive quality initiatives, pioneer modern automation (including AI-assisted workflows), and establish robust methodologies across our US and Asia design centers., * Act as the primary technical liaison between local US design teams and global cross-functional teams, translating complex specifications into seamless execution. * Provide technical support through all phases of product development: testing, yield analysis, characterization, reliability analysis, qualification, and release to manufacturing. * Adhere to strict schedule, die size, and power commitments. * Conduct detailed design reviews with internal and external customers. Digital IC Design: * Define system requirements, digital control functions, and block partitions for next-generation preamplifier products. * Perform digital logic design, Verilog coding, logic synthesis, formal verification, static timing analysis, and place and route. * Support integrating the digital core with analog circuitry into a completed integrated circuit. * Perform transistor-level high-speed digital IC design for custom cells and blocks. Digital Mixed Signal Verification: * Architect, develop, and maintain advanced UVM-based testbenches for the functional verification of complex mixed-signal ASICs. * Own verification efforts at both the block and system levels for major tape-out projects, driving functional and code coverage to closure. * Champion verification quality by integrating new methodologies (e.g., SVA, UVM/OVM) to reduce mixed-signal validation bottlenecks. * Lead initiatives to explore and integrate modern automation and AI-assisted verification workflows to accelerate testbench generation and debug efficiency. ## Related Videos - [JavaScript? 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