> Markdown version of [/jobs/ext/3431213-senior-pd-methodology-engineer-annapurna-labs-cloud-scale-machine-learning](https://www.wearedevelopers.com/jobs/ext/3431213-senior-pd-methodology-engineer-annapurna-labs-cloud-scale-machine-learning). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning - **Company:** Annapurna Labs - **Location:** Austin, TX, United States - **Experience:** Expert - **Salary:** $159,200.0 - $215,300.0 - **Contract:** Permanent contract - **Skills:** C (Programming Language), 4G (Telecommunication), Computer-Aided Design, Agile Methodology, Amazon Web Services, Wireless Broadband, Code Division Multiple Access, Cloud Computing, Computer Programming, Continuous Integration, Data Centers, Software Debugging, Logic Synthesis of Circuits, Embedded C, Emulators, Formal Verification, Field-Programmable Gate Array (FPGA), GNU Linker, Python (Programming Language), MATLAB, Machine Learning, Performance Tuning, Systems Architecture, SystemC, System on a Chip, Tcl (Programming Language), Universal Asynchronous Receiver/Transmitter, WiMAX, Scripting, Application Specific Integrated Circuits, Git, Bare Metal, Physical Design, Software Version Control - **Published:** September 9, 2026 - **Apply:** https://www.careerboard.com/us/en/find-jobs-in-United-States/-1D810F3BEDFA173120/ ## About the Role Be able to independently troubleshoot digital tool flow usage and deploy solutions; Fluent in Scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments Create Dashboard and Central reports for project tracking and visualizing QoR/stats A day in the life BASIC QUALIFICATIONS - 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience - 7+ years of digital design in communication systems experience - 7+ years of full-custom analog or RF layout experience - 7+ years of wireless communications systems and implementation experience - 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience - 7+ years of verification in communication systems experience - 5+ years of UVM, C, System C, and Scripting experience - 3+ years of emulation experience - Bachelor's degree in Electrical Engineering or a related field - Knowledge of UVM and Matlab - Knowledge of implementing chips with multiple power islands and power gating - Knowledge of multiple access systems including OFDMA, TDMA, and CDMA - Knowledge of end-to-end network system architecture from wireless physical layer to application endpoints - Knowledge of serial protocols including SPI, I2C, I3C, and UART - Knowledge of Python and Embedded C programming - Experience in communication theory, OFDM, MIMO, Digital/Wireless Communication Systems or RF engineering - Experience with current and upcoming RF standards in cellular (4G/5G), WiMAX, 802.11ad, microwave backhaul, DVB-S2/DVB-C, or related broadband wireless standards - Experience leading or solely developing methodology and scripts for physical synthesis - Experience taping out chips that have gone into high volume production - Experience developing products for volume production - Experience low power design techniques - Experience delivering products to volume production - Experience in modem L1/L2 algorithms development and architectures - Experience in developing link and system level simulators using MATLAB, Python, or C+ - Experience in test setup automation using MATLAB, Python, or Pearl - Experience with Agile, TDD, BDD, CI, and Git - Experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors - Experience leading technical initiatives and key deliverables - Experience with version control systems and CI/CD pipeline implementation - Experience in Bare Metal Environment development, including linker scripts, page tables and NVIC PREFERRED QUALIFICATIONS - Master's degree or Ph.D. degree in Electrical Engineering or related field - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs - Experience with modern ASIC/FPGA design and verification tools - Experience with SOC bring-up and post-silicon validation ## Description Custom SoCs (System on Chip) live at the heart of Amazon Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs., Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability. Fine tune cloud infrastructure to improve compute and storage utilization for physical design work. Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies.