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# Design Engineer II

- **Company:** Everforth Apex
- **Location:** Burlingame, CA, United States
- **Experience:** Experienced
- **Salary:** $235,040.0 - $255,840.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Apple IOS, Computer Engineering, Multiplexing, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), Python (Programming Language), Oracle Virtual Machine, PCI Express, Static Timing Analysis, System on a Chip, SystemVerilog, Tcl (Programming Language), Universal Asynchronous Receiver/Transmitter, Verilog, Scripting, Peripherals, Information Technology, Integration Frameworks
- **Published:** September 17, 2026
- **Apply:** https://www.dice.com/job-detail/3ca822e9-40f8-472a-b553-c6eb3d931ddb

## About the Role

Education: A Bachelor of Science in Electrical/Computer Engineering, Computer Science, or equivalent experience is required.

Experience: 4+ years as a Digital Design Engineer, with ownership of SoC/subsystem integration. Hands-on integration experience with I3C, I2C, SPI/QSPI/OSPI, and UART controllers is necessary.

Technical Skills:

 * Strong Verilog/SystemVerilog RTL coding and digital microarchitecture definition skills.
 * Python scripting is required for integration tools.
 * Practical understanding of IOs/pads used for peripherals and IO mux architecture.
 * Tcl scripting and familiarity with synthesis and static timing.
 * Experience with UPF-based simulation/low-power flows.
 * Exposure to SystemVerilog UVM/OVM.
 * Familiarity with AI-assisted code and IO system operations., * Experience with CAN / CAN-FD protocol and CAN controller integration.
 * Knowledge of I3C advanced features such as in-band interrupts, hot-join, and dynamic address assignment.
 * Experience with sensor-hub or MCU subsystem integration.
 * Experience with DFT/testability, Power-Aware GLS, and FPGA prototyping.
 * Exposure to PCIe, USB, or MIPI protocols.
 * A Master of Science in Electrical Engineering or Computer Science (MSEE/CS).

## Description

This position is for a digital design engineer to integrate the low-speed peripheral subsystem, including I3C, I2C, SPI/QSPI/OSPI, and UART controllers. The role involves managing the IO cells, pad ring connectivity, and IO multiplexing that these peripherals depend on., * Integrate I3C, I2C, SPI/QSPI/OSPI, and UART controller IPs into the peripheral subsystem and System-on-Chip (SoC) top.

 * Own IO-level integration, including pad/IO cell selection, IO mux design, and management of pad state during reset/power modes.
 * Develop glue and control logic such as bus bridging (APB/AHB/AXI), register maps, clock/reset generation, and interrupt/DMA request routing.
 * Contribute to subsystem microarchitecture and top-level RTL, and support the verification plan.
 * Extend and maintain Python-based integration and generation tooling for IO mux tables and pinmux collateral.
 * Support the RTL-to-GDS process, including constraints, synthesis, timing closure, and low-power (UPF) intent.
 * Support FPGA prototyping, bring-up, validation, and test program development.


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