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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior RTL Design Engineer in Palo Alto - **Company:** Energy Jobline - **Location:** Palo Alto, CA, United States - **Experience:** Expert - **Salary:** $120,000.0 - $225,000.0 - **Contract:** Permanent contract - **Skills:** Adobe InDesign, Artificial Intelligence, Computer Engineering, Microarchitecture, Electronic Design Automation, Emulators, Data Flow Control, Field-Programmable Gate Array (FPGA), Python (Programming Language), Static Timing Analysis, SystemVerilog, Verilog, Caching, Information Technology, Code Inspection, Hardware Acceleration, Physical Design - **Published:** September 10, 2026 - **Apply:** https://www.energyjobline.com/job/senior-rtl-design-engineer-palo-alto-31579098 ## About the Role * Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. * 8+ years of industry experience in RTL design, microarchitecture, and architecture development. * Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies). * Hands-on experience with one or more of the following subsystems: scheduling fabrics, high-performance interconnects, DMA engines, memory controllers, or datapath/control logic. * Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines. * Familiarity with timing constraints, physical design considerations, and EDA flows. * Hands-on experience with simulation, synthesis, linting, and static timing analysis tools. * Strong problem-solving and communication skills with ability to work in cross-functional teams., * Familiarity with network-on-chip (NoC) architectures. * Expertise in low-power design techniques (clock gating, power gating, multi-voltage domains). * Experience with timing closure in advanced technology nodes and collaboration with physical design teams. * Strong skills in performance modeling and trade-off analysis (PPA optimization). * Hands-on experience with emulation/FPGA prototyping for early RTL validation. * Familiarity with AI, DSP, or other parallel compute architectures. * Strong scripting ability (Python or similar) for design automation and productivity. ## Description this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. RTL Design at Mythic: At Mythic, our RTL design team is at the heart of transforming our custom digital dataflow architecture into working silicon. This architecture incorporates a novel scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines. Together with our Analog Compute Engines, these critical technologies enable unprecedented efficiency for modern AI workloads. RTL engineers take ownership of microarchitecture and RTL implementation, designing high-performance, low-power logic that drives our breakthrough AI hardware. The team works closely with architecture, custom analog IP, compiler, verification, emulation, and post-silicon groups to ensure every component integrates seamlessly into the full system. Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply both creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness. We welcome engineers at all levels who are excited to tackle challenging design problems and play a key role in building the next of AI compute hardware. Responsibilities * Design and implement RTL for Mythic's next- AI processor. * Contribute to the development of a novel digital dataflow architecture, including a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines. * Develop and optimize high-performance, low-power components such as datapaths, controllers, memory subsystems, and interconnects. * Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness. * Drive timing closure by working closely with synthesis and physical design teams. * Participate in design reviews and contribute to improving RTL coding practices and methodologies. ## Related Videos - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) - [Thinking Differently - How to Make Money from Cyber Attacks & Cheats](https://www.wearedevelopers.com/videos/745-thinking-differently-how-to-make-money-from-cyber-attacks-cheats) - [HTTP headers that make your website go faster](https://www.wearedevelopers.com/videos/1676-http-headers-that-make-your-website-go-faster) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [WeAreDevelopers LIVE – Web Scraping, Agents, Actors and more](https://www.wearedevelopers.com/videos/1764-wearedevelopers-live-web-scraping-agents-actors-and-more) - [Event based cache invalidation in GraphQL](https://www.wearedevelopers.com/videos/433-event-based-cache-invalidation-in-graphql) ## Related Articles - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Where To Find Software Engineering Jobs](https://www.wearedevelopers.com/magazine/396-where-to-find-software-engineering-jobs) - [The Most Popular IT Jobs on the Market](https://www.wearedevelopers.com/magazine/376-the-most-popular-it-jobs-on-the-market) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers)