> Markdown version of [/jobs/ext/3450029-senior-engineer-pll-design](https://www.wearedevelopers.com/jobs/ext/3450029-senior-engineer-pll-design). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Engineer, PLL Design - **Company:** Samsung - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $138,000.0 - $206,000.0 - **Contract:** Temporary contract - **Skills:** Computer-Aided Design, Artificial Intelligence, Software Debugging, Systems Theories, MATLAB, Monte Carlo Methods, SystemVerilog, Verilog - **Published:** September 21, 2026 - **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/18413448?backUrl=%2Fcareer%2F18413448%2FSenior-Engineer-Pll-Design-California-San-Jose ## About the Role * Bachelor's with 5+ years of experience or Master's with 3+ years of experiences or PhD with 0 years of experience in a related field. * Extensive hands-on experience designing PLLs in deep sub-micron CMOS (5nm-28nm), including at least one of: integer-N, fractional-N, digital PLL, or sub-sampling PLL topologies * Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs * Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator * Strong Matlab/Simulink skills for behavioral modeling and system-level analysis * Familiarity with Verilog/SystemVerilog for mixed-signal simulation * Solid understanding of layout-sensitive design and ability to guide critical PLL layout (LC tank, charge pump, reference path) * Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment * Experience with RTL design (Verilog/SystemVerilog) to implement PLL-related digital calibration circuits, including frequency calibration, phase calibration, and background self-calibration logic * Excellent problem-solving, analytical, and communication skills ## Description Samsung Semiconductor Inc is looking for a talented Senior/Staff PLL Designer with strong background and hands-on experience in PLL and clock generation circuit design. The candidate will work on the design and development of high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications in advanced deep-submicron CMOS technologies. What You'll Do * Design PLLs and clock generation circuits (integer-N, fractional-N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications * Design critical PLL building blocks including VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators * Perform PLL system-level modeling, noise analysis, and jitter budgeting using Matlab/Simulink * Drive design verification including transistor-level simulation, Monte Carlo analysis, and silicon correlation * Collaborate with digital, layout, and systems teams to deliver PLL IPs meeting performance, power, and area targets * Support bring-up, characterization, and debug of silicon prototypes in the lab, At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. 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