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# Mixed-signal Design Architect, HBM Architecture

- **Company:** Micron Technology, Inc.
- **Location:** Folsom, CA, United States
- **Experience:** Expert
- **Salary:** $146,000.0 - $297,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Dynamic Random-Access Memory, Perl (Programming Language), Hardware Description Language, Python (Programming Language), Verilog, Scripting, Information Technology
- **Published:** September 2, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3379548244&tx=IT8578TYV&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Experience with analog and/or mixed-signal design, including simulation and floorplanning.
 * Experience with transistor-level simulation (e.g., FineSim, HSPICE) including corner analysis.
 * Ability to analyze architecture tradeoffs and use findings to develop specifications.
 * Experience with power delivery analysis, tradeoffs, constraints, and challenges.

Preferred Qualifications:

 * Familiarity with DRAM or high-performance, 3D-stacked memory devices like HBM.
 * Contributions to thermal and/or power delivery solutions for stacked architectures.
 * Experience in one or more scripting languages (e.g., Python, Perl) and hardware description language (e.g., Verilog).
 * A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
 * 5+ years of proven experience delivering mixed-signal circuit designs, 3D-stacked memory or logic designs, or complex packaging architectures.

## Description

* Design, optimize, and simulate critical analog and/or mixed-signal circuits.
 * Architect and design power delivery for high-performance, stacked memories.
 * Analyze, specify, and prototype on-/off-chip interfaces.
 * Perform timing, area, power, and complexity analysis for high-performance, low-power circuits.
 * Define architectures for improved thermal management.
 * Conduct pathfinding activities for future-generation stacked-memory products.
 * Compose and maintain clear architecture documentation.