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# CPU Performance Architect

- **Company:** Google LLC
- **Location:** Mountain View, CA, United States
- **Experience:** Expert
- **Salary:** $163,000.0 - $236,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Data Analysis, ARM Architecture, C++ (Programming Language), Computer Engineering, Device Drivers, Python (Programming Language), Linux Kernel, Scripting, Information Technology
- **Published:** September 10, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=2a6a089c4bba226f

## About the Role

* Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
 * 8 years of experience with performance analysis, microarchitectural bottleneck isolation, and workload characterization.
 * Experience with C/C++ for architectural modeling and scripting languages (specifically Python) for data analysis and automation frameworks., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
 * Experience with the ARM instruction set architecture (ISA) and ecosystem.
 * Experience characterizing and optimizing mobile or client platform power/performance and thermal management states (e.g., DVFS).
 * Understanding of low-level system software components, including the Linux kernel, device drivers, power management frameworks, and runtimes.

## Description

* Lead deep-dive microarchitectural analysis on silicon to isolate and quantify pipeline stalls, memory hierarchy bottlenecks, and instruction-level inefficiencies to drive root-cause resolution.
 * Design, build, and execute advanced power and performance experiments on physical silicon to rigorously correlate pre-silicon projections with post-silicon reality across general-purpose and AI/ML compute workloads.
 * Develop and maintain early-stage power and performance models to evaluate complex architectural "what-if" scenarios, driving hardware-software co-optimization.
 * Partner closely with lead CPU architects and cross-functional teams to define dynamic, realistic power and performance goals for future Google silicon.


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