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# ASIC Architect

- **Company:** Redline Group
- **Location:** Oxford, UK
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Electronic Design Automation, Firmware, Data Flow Control, Python (Programming Language), Systems Architecture, Application Specific Integrated Circuits, Instruction Set Architecture, Reasoning Engines, Physical Design
- **Published:** October 2, 2026
- **Apply:** https://www.constructionjobboard.co.uk/system/classifieds/application_redirect/?listing_id=3776801

## About the Role

* Proven architectural ownership of at least one ASIC taken successfully to tape-out, ideally within compute accelerators, inference engines or DSP applications.
 * Strong hands-on experience with performance modelling, simulation and architectural trade-off analysis using Python, C++ or similar languages.
 * Experience with industry-standard semiconductor tool flows such as Synopsys, Cadence or Siemens EDA tools.
 * Solid understanding of timing, power and area optimisation at the architectural level.
 * Experience defining hardware/software interfaces and collaborating with firmware and compiler teams.
 * Strong RTL design knowledge and experience defining verification strategies from an architectural perspective.

This is a fantastic opportunity to play a pivotal role in developing revolutionary computing technology, influencing product direction and driving innovation from concept through to silicon deployment.

## Description

Great opportunity for an experienced ASIC Architect to join an innovative next-generation computing company and taking ownership of the architecture and development of a cutting-edge probabilistic computing processor. This is a highly influential role where you will lead ASIC architecture from algorithm and ISA definition through to tape-out and silicon bring-up., * Own the end-to-end ASIC architecture of a probabilistic computing processor, from algorithm understanding through to tape-out.

 * Define system architecture, instruction set architecture (ISA) and dataflow models based on workload requirements.
 * Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements.
 * Build functional simulations and performance models to guide architectural decisions.
 * Conduct timing, power and area trade-off analysis with strong physical design awareness.
 * Define detailed microarchitecture specifications, including memory hierarchy, connectivity and interface requirements.
 * Lead internal IP development and evaluate third-party IP solutions.
 * Guide designs through verification, sign-off, tape-out and silicon bring-up.