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# Digital Design Verification Engineer (UVM)

- **Company:** TMC
- **Location:** Eindhoven, Netherlands
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Digital Technology, Field-Programmable Gate Array (FPGA), PCI Express, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Serial Peripheral Interface
- **Published:** June 4, 2026
- **Apply:** https://nl.indeed.com/viewjob?jk=d936361acaadfcad

## About the Role

Do you have experience in Verilog?, Do you have a Master's degree?, We are looking for a highly motivated Digital Design Verification Engineer with strong expertise in SystemVerilog and UVM methodology, capable of building verification environments from scratch., > Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field > Minimum 5 years of industry experience in digital IC/SoC/FPGA verification > Strong hands-on experience with: SystemVerilog & UVM - including building testbenches from scratch > Proven experience in: constrained-random verification, functional coverage and assertion-based verification, and debugging complex digital systems > Familiarity with standard interfaces (e.g., AXI, APB, SPI, I2C, PCIe, or similar) > Experience with industry-standard simulators (e.g., Questa, VCS, Xcelium) > Solid understanding of digital design concepts and RTL (Verilog/VHDL)



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