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# Digital Design Engineers

- **Company:** Eu Recruit
- **Location:** AMSTERDAM, Netherlands
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Electronic Design Automation, Python (Programming Language), Static Timing Analysis, System on a Chip, SystemVerilog, Tcl (Programming Language), VHSIC Hardware Description Language (VHDL), Linux Virtual Server, Scripting, Backend, Front End Software Development, Physical Design, Cts+
- **Published:** June 4, 2026
- **Apply:** https://eu-recruit.com/jobs/senior-digital-design-engineer-6/

## About the Role

Experience with EDA tools from Cadence, Synopsys or Mentor for logic synthesis, static timing analysis, and
backend implementation.

 - Familiarity with low-power design techniques, clock domain crossing (CDC), and hierarchical SoC design.
 - Hands-on experience in physical implementation (floorplanning, P&R, CTS, STA, DRC, LVS).
 - Experience with modern process nodes, especially 22FDX, 16/12nm FinFET, or similar.
 - Good understanding of mixed-signal integration, top-level assembly, and testability concepts (DFT is a plus).
 - Strong problem-solving skills, attention to detail, and ability to work independently., Mid-Level: 3-5 years of relevant experience in digital IC design.
 - Senior-Level: 6+ years, with ownership of IP/SoC blocks or backend flows.
 - MSc or PhD in Electrical Engineering, Microelectronics, or related field.

## Description

We are looking for Digital Design Engineers with strong expertise in either frontend RTL design, backend physical
implementation, or ideally both.

You will contribute to the development of high-performance digital and mixedsignal ICs in advanced technology nodes such as 22FDX and other FinFET/FD-SOI processes.

We are hiring for both Mid-Level and Senior-Level roles, depending on experience and leadership capabilities.
Responsibilities

 - OwnRTL design and micro-architecture of digital subsystems (e.g., DSP blocks, control logic, interfaces).
 - Develop and optimize backend flow, including synthesis, floorplanning, placement and routing (P&R), timing
closure, and signoff (STA, LVS, DRC).

 - Perform logic synthesis and work with physical design teams to ensure a clean handoff and alignment across
digital and mixed-signal boundaries.

 - Support integration of digital blocks with analog/mixed-signal subsystems.
 - Generate documentation, testbenches, and support post-silicon bring-up and debugging.
 - (Senior level) Lead block-level architecture, mentor junior designers, and guide design methodology decisions.
Your Profile

 - Strong proficiency in RTL design using SystemVerilog/VHDL, digital verification, and scripting (Python, Tcl, etc.).


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