> Markdown version of [/jobs/ext/3540327-asic-digital-design-technical-leader](https://www.wearedevelopers.com/jobs/ext/3540327-asic-digital-design-technical-leader). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# ASIC Digital Design Technical Leader

- **Company:** Cisco Systems, Inc.
- **Location:** Carlsbad, CA, United States
- **Experience:** Expert
- **Salary:** $177,600.0 - $257,400.0
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), System on a Chip, Systems Integration, Application Specific Integrated Circuits, Backend
- **Published:** October 2, 2026
- **Apply:** https://dejobs.org/x/x/FCDA534118674A8CA203EE0B3F305454/job/

## About the Role

* Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience.
 * Prior digital design experience working with FSMs, CPU sub-systems, complex SoCs, and FPGA validation
 * Prior experience in managing the complete ASIC/SoC design flow
 * Prior experience with one more more key bus and interface protocols (e.g., SPI, I2C, APB, AXI) as well as high-speed SerDes, Ethernet, and/or D2D PHY IP., * End-to-End Silicon Lifecycle & Architecture: Prior experience leading the architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff, through post-silicon FPGA prototyping, lab validation, and ATE bring-up.
 * Specification & Microarchitecture Design: Prior experience developing top and block-level specifications for high-speed datapath and low-speed control planes, including power/timing budgeting, feedback/control system stability, and hardware vs. firmware trade-offs.
 * Verification, Simulation & IP Integration: Prior experience reviewing verification coverage metrics, independently debugging verification issues, supporting firmware-based verification/architecture, and integrating SerDes and DSP IP.
 * Implementation, Backend & Automation: Hands-on experience with backend implementation activities-including synthesis, timing closure, DFT, low-power design, design automation scripting, and QOR metric processing.
 * Technical Leadership: 6+ years in a technical leadership role collaborating across cross-functional engineering teams to resolve technical trade-offs and complex design issues.