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# RTL DESIGN ENGINEER (SILICON ENGINEERING)

- **Company:** Space Exploration Technologies Corp.
- **Location:** Redmond, WA, United States
- **Experience:** Expert
- **Salary:** $165,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Electronic Design Automation, Hardware Description Language, Python (Programming Language), Systems Integration, Scripting, Application Specific Integrated Circuits, Information Technology
- **Published:** October 2, 2026
- **Apply:** https://startup.jobs/sr-asic-design-engineer-silicon-engineering-spacex-10250321

## About the Role

* Bachelor's degree in electrical engineering, computer engineering, or computer science
 * 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

 * Ability to solve complex problems including clock domain crossings and power optimization
 * ASIC/SoC system integration experience
 * Experience with embedded CPU subsystems
 * Experience with standard bus protocols (e.g. AXI, AHB, etc.)
 * Experience with high speed and low power design techniques
 * Scripting skills (e.g. Python, etc.)
 * Experience with EDA tools such as HDL simulators and HDL Lint tools
 * Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
 * Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

 * Ability to work extended hours or weekends as needed for mission critical deadlines, * To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

## Description

* Evaluate architectural trade-offs based on features, performance requirements and system limitations
 * Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
 * Work closely with verification team to ensure all aspects of the design are covered and verified
 * Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
 * Participate in silicon bring-up and validation