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# Staff HBM Design Architect

- **Company:** Micron Technology, Inc.
- **Location:** Folsom, CA, United States
- **Experience:** Experienced
- **Salary:** $150,000.0 - $323,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Very-Large-Scale Integration, Dynamic Random-Access Memory, Electronic Design Automation, Perl (Programming Language), Python (Programming Language), Cadence Virtuoso, Tcl (Programming Language), Linux Virtual Server, Physical Verification
- **Published:** October 2, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3414910720&tx=CT2927TTZ&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related technical field
 * 4+ years of semiconductor physical layout experience with analog, digital, or mixed-signal blocks
 * Proficiency with Cadence Virtuoso VLE/VXL and Siemens Calibre DRC/LVS
 * Experience converting schematics into manufacturable layouts and completing physical verification
 * Ability to explain layout constraints and tradeoffs to design, architecture, and cross-functional teams, * Master's degree in Electrical Engineering, Microelectronics, VLSI, or a related field
 * 7+ years of full-custom layout experience with HBM, DRAM, or high-speed memory products
 * Experience with JEDEC HBM specifications, TSV-based 3D stacking, full-chip integration, and macro floorplanning
 * Proficiency with SPICE, FineSim, or HSPICE and Python, SKILL, Perl, or Tcl
 * Experience influencing product architecture through layout analysis and using AI-assisted layout workflows

## Description

As a Custom Layout Architecture Engineer , you will use physical layout expertise to inform HBM architecture and implementation decisions from concept through tapeout. You will work with design, architecture, process, verification, and product engineering teams to balance performance, power, area, routability, and manufacturability. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making., * Assess HBM architecture choices through layout feasibility, floorplanning, and performance, power, and area analysis

 * Lead custom layout and full-chip integration for analog, mixed-signal, digital, and memory blocks
 * Resolve antenna, latch-up, ESD, electromigration, IR drop, routability, and power-delivery constraints
 * Complete DRC/LVS, parasitic extraction, post-layout validation, and tapeout support using industry-standard EDA tools
 * Build scripts and automation that improve layout quality, verification, and design-cycle time