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# Member of Technical Staff, SoC Power and Physical Architect, Next- HBM Architecture in , United States

- **Company:** Energy Jobline
- **Location:** United States
- **Experience:** Expert
- **Salary:** $191,000.0 - $334,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Data Driven Tests, Static Timing Analysis, Information Technology
- **Published:** October 2, 2026
- **Apply:** https://www.energyjobline.com/job/member-technical-staff-soc-power-and-physical-architect-next-hbm-architecture-united-states

## About the Role

Experience with circuit design, including IP interface requirements, power delivery behavior, and clocking constraints.
Familiarity with chip-level thermal analysis and power hotspot mitigation strategies.
Strong experience reasoning about interconnects and frequency vs. energy/power tradeoffs.
Experience with synthesis, static timing analysis, and relevant EDA toolsets: PrimePower, PrimeShield, RedHawk, and ICC2.
Minimum Qualifications

Experience with high-bandwidth memory (HBM) architectures.
Ability to influence decisions through data-driven analysis and clear communication.
A Masters or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
8+ years of industry experience delivering SoC hardware designs.
Job Profile(s)

## Description

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications.
Responsibilities

Define clocking architectures, power sequencing, power delivery, and on-die signal interfaces.
Define and analyze on-die power delivery networks (PDN) and full-chip thermal implications, including power hot-spot identification and mitigation.
Define DFT architectures (e.g., scan chain topology) and set verification requirements.
Define SoC floorplans in collaboration with physical designers.
Compose and maintain clear SoC physical documentation.