> Markdown version of [/jobs/ext/3557306-design-for-testability-dft-engineer](https://www.wearedevelopers.com/jobs/ext/3557306-design-for-testability-dft-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Design for Testability (DFT) Engineer - **Company:** L&T Technology Services - **Location:** San Francisco, CA, United States - **Experience:** Experienced - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Bash Shell, Computer Programming, Computer Engineering, Software Debugging, Perl (Programming Language), Hardware Description Language, IEEE Standards Association, Joint Test Action (IEEE Standards), Python (Programming Language), SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, Physical Design - **Published:** October 2, 2026 - **Apply:** https://www.dice.com/job-detail/520193e8-a892-4e6d-92c7-bbdaff6de5a1 ## About the Role * Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field. * Experience: 3+ years of hands-on DFT implementation and verification experience on complex ASIC/SoC designs. * EDA Tool Expertise: Strong proficiency in at least one major EDA vendor DFT suite: + Siemens/Mentor: Tessent (Tessent Scan, FastScan, TK/TestKompress, Tessent Shell, IJTAG, MemoryBIST). + Synopsys: TestMAX (DFTMAX, TetraMAX, SMS/MBIST). + Cadence: Modus DFT Software. * Programming/Scripting: Hands-on experience with TCL, Perl, Python, or Bash for flow automation. * Hardware Description Languages: Proficient in Verilog, SystemVerilog, and VHDL. Preferred / Plus Skills * Experience with advanced nodes (5nm, 3nm, 2nm) and multi-die / 2.5D / 3D chiplet architectures. * Hands-on experience with Silicon Bring-Up and ATE pattern validation in a lab/test house environment. * Deep understanding of Fault Diagnostics and yield learning workflows. * Familiarity with Automotive Safety standards (ISO 26262) and functional safety (FuSa) DFT mechanisms. ## Description L&T Technology Services (LTTS) is looking for talented, hands-on DFT Engineers to join our semiconductor engineering team in the Bay Area, CA. In this role, you will work on cutting-edge, complex SoCs targeting AI, Automotive, Networking, and Next-Gen Compute applications. You will be responsible for defining, implementing, and verifying state-of-the-art DFT architectures across advanced technology nodes., * DFT Architecture & Implementation: Implement and verify Scan, Compression, ATPG, MBIST, LBIST, and IEEE standards (1149.1 JTAG, 1500, 1687 IJTAG, 21686). * ATPG & Fault Coverage: Generate, debug, and optimize ATPG patterns (Stuck-at, At-Speed / Transition, Cell-Aware, Path Delay) to achieve high fault coverage metrics. * Memory BIST & Logic BIST: Insert and verify MBIST/LBIST controllers across complex multi-frequency clock domains and multi-die / chiplet architectures. * Simulation & Timing Verification: Perform zero-delay and timing-annotated (SDF) pattern simulations, debug timing violations, and collaborate with Physical Design (PD) teams on DFT constraints and STA closure. * Silicon Bring-up & ATE Support: Assist product and test engineering teams during silicon bring-up, pattern translation (WGL/STIL), and failure analysis on Automated Test Equipment (ATE). ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Old tools, new tricks](https://www.wearedevelopers.com/videos/1916-old-tools-new-tricks) - [JavaScript? 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