> Markdown version of [/jobs/ext/3564311-technical-lead-engineer-power-validation-characterization](https://www.wearedevelopers.com/jobs/ext/3564311-technical-lead-engineer-power-validation-characterization). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Technical Lead Engineer - Power Validation & Characterization - **Company:** The Meta Game, Inc. - **Location:** Sunnyvale, CA, United States - **Experience:** Expert - **Salary:** $212,000.0 - $294,000.0 - **Contract:** Permanent contract - **Skills:** Data Analysis, Computer Engineering, Data Centers, Software Debugging, Network Interface Controllers, Firmware, Field-Programmable Gate Array (FPGA), Design of User Interfaces, Hardware Design, Python (Programming Language), Operational Databases, Application Specific Integrated Circuits, Information Technology, Bare Metal, Data Pipelines - **Published:** October 3, 2026 - **Apply:** https://dejobs.org/x/x/694C5A2EA01B471ABADDB04A4BF9C565/job/ ## About the Role 12. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 13. 12+ years of relevant industry experience 14. Demonstrated hands-on validation and characterization experience on complex ASICs, SoCs, NICs, or high-speed interfaces 15. Proven experience with PVT (Process / Voltage / Temperature) characterization 16. Ability to read and reason about schematics and either power delivery networks or high-speed interface implementations 17. Proficiency in Python for test development, lab automation, and/or data analysis 18. Hands-on lab experience with domain-relevant instrumentation, 19. Experience building large-scale lab automation frameworks and data pipelines for characterization data 20. Familiarity with on-die telemetry, ring-oscillator data, eFuse-based binning, and adaptive voltage scaling 21. Experience developing hardware for data center deployment 22. Experience taking a custom ASIC from first silicon through high-volume production 23. Experience with custom silicon programs 24. Hands-on lab experience with domain-relevant instrumentation for Power - SMUs, electronic loads, power analyzers, scopes, current probes, thermal chambers / forced-air and liquid-cooled setups 25. plus experience with multi-kW systems 26. Experience with liquid-cooled and high-TDP (2kW+) accelerator or networking platforms 27. Experience working directly with ODMs, test houses, and silicon vendors 28. Advanced degree (MS or PhD) in Electrical Engineering, Computer Engineering, or a related field 29. Experience across both pre-silicon (emulation/FPGA) and post-silicon validation ## Description Meta's Infrastructure team delivers scalable and reliable custom ASIC solutions to meet Meta's data center needs. Ramping to production and solving data center scaling and deployment challenges requires a systems-based approach to silicon bring-up and validation.The team works on productization: early architecture and design inputs, pre-silicon validation on emulation platforms, first-silicon bring-up, and post-silicon characterization across process, voltage, and temperature corners. We write tests, build bare-metal environments and reusable frameworks that scale from pre-silicon platforms to large fleets of ASICs in the lab, and we build and maintain extensive lab automation to do it at volume and velocity., 1. Own the end-to-end validation and characterization strategy for Meta custom silicon programs in your domain, from pre-silicon emulation through post-silicon bring-up and PVT characterization 2. Define the test plan: measurement and benchmarking methodology, instrumentation, functional and performance coverage, corner coverage across process/voltage/temperature, and pass/fail criteria 3. Establish and document best practices for measurement rigor, accuracy, and correlation across bench, emulation, and ATE/production data 4. Drive validation of domain feature sets (power or networking) on emulation platforms pre-silicon and on real silicon post-silicon 5. Review schematics, power delivery networks, high-speed interface designs, and board/platform configurations with hardware and design teams 6. provide early design and debuggability inputs 7. Write and review automation and analysis code that scales characterization from a single bench to many units in the lab 8. Lead debug of complex cross-stack issues - silicon, firmware, driver, board, thermal, and fabric/switch layers - and drive root cause to closure with design, software, hardware, ODM, and vendor partners 9. Provide technical guidance and planning for a team of validation engineers 10. mentor engineers and improve standards for data quality and rigor 11. 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