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# Senior Logic Design Engineer

- **Company:** Microsoft
- **Location:** Raleigh, NC, United States
- **Experience:** Expert
- **Salary:** $119,800.0 - $234,700.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Artificial Intelligence, Microsoft Online Services, Computer Engineering, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), Subsystems, System on a Chip, SystemVerilog, Tcl (Programming Language), Verilog, Information Technology, Power Analysis (Cryptography), Code Inspection, Front End Software Development, Physical Design
- **Published:** October 6, 2026
- **Apply:** https://www.jobmonkeyjobs.com/career/28081404/Senior-Logic-Design-Engineer-North-Carolina-Raleigh-1210

## About the Role

* Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
 + OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
 + OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
 + OR equivalent experience., * Knowledge of logic design flow including Low Power Analysis, UPF, RTL coding, Synthesis, timing constraints, timing closure.
 * Demonstrated expertise in Computer Architecture, Digital Design, IP/SoC design principles as part of SoC and/or IP development.
 * Have prior experience in Low Power architecture microarchitecture with implementation and qualification via writing UPF
 * Highly Proficient in Verilog/System Verilog coding constructs.
 * Knowledge of front-end tools ( VCLP, Verilog simulators, Connectivity tools, low power static checkers, linting)
 * Demonstrated experience and knowledge of clock crossings, and power/UPF in design
 * Ability to write scripts using Perl, Tcl, Python etc.
 * Familiarity with Industry standard interface protocols (ARM) is a plus.
 * Familiarity with Formal Equivalence Verification and Power Analysis is a plus.
 * Verbal and written communication skills.

Screening Requirements

 * Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
 * This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

## Description

We are looking for a Senior Logic Design Engineer to support our micro-architecture, RTL implementation, IP & subsystem SOC development design while being attentive to quality assurance for our projects. This is a key role withindesign domain especially focused on Low Power Design (LP and UPF) ensuring SOC is meeting high standards in design and quality., In this role, you will be an integral part of Logic Design Team and will be expected and able to complete the following responsibilities:

 * Develop and implement micro-architectural specification focusing on Low Power
 * Continue to grow your micro-architectural knowledge and contribute to unit, sub-system and SOC micro-architecture
 * Development and Integration of various functional block RTL
 * Perform design quality checks such as Timing closure, Lint, CDC, Synthesis, Low Power Intent

 * Utilize AI for gaining efficiency within process and development
 * Interface with verification team to ensure functional correctness. Interface with performance modeling, physical design, design-for-test, and other teams to deliver qualified physical partitions evaluating tradeoffs and delivering high-quality design

 * Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary. Automate tasks using scripting for efficiency
 * Delight your customers by providing high-quality functional blocks on schedule and with professional integrity

 * Challenge the status quo with growth mindset.
 * Mentor team members and summer interns for a growing team