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# Hardware Engineer, AI Accelerator Power Design

- **Company:** Facebook Inc.
- **Location:** Austin, TX, United States
- **Experience:** Experienced
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Software Debugging, Schematic Capture, Application Specific Integrated Circuits, Modeling and Simulation, Hardware Acceleration, Physical Design, Ansys
- **Published:** October 7, 2026
- **Apply:** https://www.jobmonkeyjobs.com/career/28084782/Hardware-Engineer-Ai-Accelerator-Power-Design-Texas-Austin-7418

## About the Role

* BS in Electrical Engineering or equivalent, plus 8+ years of hardware power design experience (MS + 6 years, or PhD + 4 years)
 * DC/DC power electronics design experience: specification and requirement setting, topology and component selection, regulation scheme definition, and bring-up/validation/troubleshooting
 * Demonstrated efficiency design practice in high-power systems: setting efficiency targets, component selection for efficiency, and trade-offs under space and thermal limitations
 * Deep hands-on PCB physical design experience: PDN design and optimization, power plane design, stack-up definition, placement analysis, and power circuit layout best practices
 * Power integrity expertise: circuit modeling and simulation used to drive design iteration, with proven simulation-to-lab closure, and knowledge of where/how to measure power effectively in DC/DC designs
 * Experience with high-current, low-voltage rails and the decoupling/noise strategy for large digital loads (ASIC, SoC, GPU, or similar)
 * Proficiency with schematic capture and layout tools, and PI/PDN simulation tools (e.g., Ansys SIwave/Q3D, Cadence Sigrity, or equivalent)
 * Lab proficiency: oscilloscopes, electronic loads, thermal imaging, and measurement techniques appropriate to high-current power rails
 * Track record operating independently on ambiguous problems and driving cross-functional efforts to resolution without guidance, * Experience supporting multiple complex programs in parallel, balancing competing schedules and priorities across concurrent design cycles
 * Experience with thermal/mechanical co-design in dense liquid-cooled or air-cooled modules
 * Experience with 1kW+ accelerator or ASIC-class power delivery, including 48V architectures
 * Experience defining team-wide design standards, review processes, or automation
 * Experience driving vendor and ODM development cycles end to end, including technology roadmap engagement with silicon and passive component suppliers
 * Experience with vertical power delivery, power modules integrated near-die, or backside power delivery concepts
 * Awareness of power delivery technology trends for 1kW-and-beyond ASICs

## Description

The ARD team designs accelerator reference platforms for Meta's AI hardware roadmap. This role owns the board-level power delivery system end to end for multi-kilowatt accelerator modules - DC/DC converter design and the PCB power delivery network, from topology and component selection through PDN architecture, stack-up, placement, layout, power integrity simulation, and lab correlation. You will work closely with ASIC, HW platform, thermal, SI/PI, and mechanical teams to co-design the power path, and directly with top-tier external partners and ODMs to drive designs from concept through production., * Own the module power delivery system end to end: DC/DC topology and component selection, regulation scheme, and the PCB power delivery network

 * Set power specifications and efficiency targets for high-power ASIC loads
 * make component and architecture choices against space, thermal, cost, and production-reliability constraints
 * Own PCB physical design of the power path: PDN architecture and optimization, power plane design, stack-up definition, placement analysis, and power circuit layout best practices
 * Define and close power integrity targets through modeling and simulation (DC IR drop, AC impedance, transient response), and correlate simulation against lab measurements
 * Partner with ASIC teams on package/board co-design, including socket and interposer power path, current density, and on-die vs. on-board decoupling allocation
 * Lead board bring-up, validation, and debug of power rails
 * define measurement methodology for high-current, low-voltage rails
 * Drive design reviews with ODM/CM partners
 * establish layout and DFx best practices adopted across the broader team
 * Explore and develop leading-edge DC/DC and power delivery technologies (e.g., vertical power delivery, near-die power modules) with industry partners
 * Contribute to design guidelines, review checklists, and tooling that raise the quality bar across ARD