> Markdown version of [/jobs/ext/3605832-digital-design-engineer](https://www.wearedevelopers.com/jobs/ext/3605832-digital-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Digital Design Engineer - **Company:** LAINE RECRUITING, LLC - **Location:** Rochester, NY, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Altium Designer, Computer Engineering, Software Debugging, Digital Electronics, Field-Programmable Gate Array (FPGA), OrCAD, Schematic Capture, Signal Integrity, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL) - **Published:** October 7, 2026 - **Apply:** https://www.thejobnetwork.com/job/76c583a4-3b4c-40dc-8989-654bb690a843/senior-digital-design-engineer ## About the Role * Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline. \n * Significant experience designing complex digital electronics and printed circuit boards. \n * Hands-on experience with schematic capture and multilayer PCB design. \n * Strong understanding of high-speed digital interfaces and board-level design considerations. \n * Experience taking hardware through prototype bring-up, debug, verification, and production transition. \n * Strong lab skills and experience troubleshooting complex electronic systems. \n * Ability to work effectively across multiple engineering disciplines. \n * Strong communication skills and the ability to explain technical decisions clearly. \n * Ability to work in the U.S. without sponsorship and meet applicable customer or program requirements. \n, * Experience with Siemens PADS, Xpedition, Altium, OrCAD, Cadence Allegro, or similar PCB design tools. \n * Experience with FPGA-based designs and VHDL, Verilog, or SystemVerilog. \n * Experience with RF, embedded systems, or communications products. \n * Experience with signal integrity and power integrity analysis.