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# Senior Digital Verification Engineer

- **Company:** Insight Global
- **Location:** Chandler, AZ, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Communications Protocols, Logic Synthesis of Circuits, Perl (Programming Language), Emulators, Formal Verification, Field-Programmable Gate Array (FPGA), Python (Programming Language), Oracle Virtual Machine, PCI Express, Shell Script, SystemVerilog, Universal Asynchronous Receiver/Transmitter, Verilog
- **Published:** October 8, 2026
- **Apply:** https://dejobs.org/x/x/C5EFF0A56E2B4894829FC5B9E2FA98E3/job/

## About the Role

BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years of semiconductor industry experience.

Strong understanding of digital design fundamentals, FSMs, CDC, reset architecture, low-power design, and SoC integration.

Expertise in Verilog, SystemVerilog, UVM/OVM, and class-based verification methodologies.

Strong knowledge of constrained-random, coverage-driven verification, regression automation, and verification signoff.

Hands-on experience developing testbenches, drivers, monitors, scoreboards, assertions, and reusable verification IP.

Experience with SystemVerilog Assertions (SVA), formal verification techniques, and low-power verification methodologies such as UPF/CPF.

Knowledge of industry-standard protocols including AMBA, I²C, SPI, UART, CAN, LIN, DDR, and PCIe.

Proficiency in Python, Perl, and UNIX/Linux shell scripting for automation. Familiarity with FPGA, emulation, or prototyping platforms such as HAPS, Palladium, or Zebu is a plus.

Understanding of PMIC architectures and power management concepts is highly desirable.

## Description

We are seeking a Senior Digital Verification Engineer to develop next-generation Power Management ICs (PMICs) for automotive and industrial applications. This role will lead digital verification from architecture review through verification signoff, ensuring functionality, quality, reliability, and compliance.