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# Staff Digital Design Engineer

- **Company:** Innatera Nanosystems
- **Location:** London, UK (Remote available)
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Code Review, Communications Protocols, Software Debugging, Software Design Documents, Logic Synthesis of Circuits, Firmware, Static Timing Analysis, Subsystems, SystemVerilog, Systems Integration, Verilog, Application Specific Integrated Circuits, Backend, Front End Software Development, Physical Design
- **Published:** June 24, 2026
- **Apply:** https://uk.indeed.com/viewjob?jk=b85b9d38c66e927e

## About the Role

Do you have experience in Verilog?, * 7+ years of hands-on experience in ASIC digital design, with a focus on complex IP blocks and SoC-level integration;

 * Strong RTL design and debugging skills in SystemVerilog/Verilog;
 * Deep understanding of SoC architecture, memory-mapped bus interfaces, and IP integration flows;
 * Experience with Cadence tools and EDA flows;
 * Proven ability to define PPA goals, perform synthesis and static timing analysis;
 * Familiarity with DFT, gate-level simulations, and low-power design methodologies;
 * Comfortable with drafting specifications, design documents, and reviewing hardware/software integration requirements;
 * Have exposure to functional verification and writing or reviewing testbenches.

Nice to have:

 * Familiarity with communication protocols (SPI, I2C, AMBA, OBI), DFT, and backend hand-off

WHAT YOU NEED TO SUCCEED:

 * Excellent problem-solving and debugging skills;
 * Strong documentation habits and ability to formalize design specifications;
 * A collaborative, proactive mindset and willingness to work across disciplines;
 * Experience mentoring or coaching engineers is a plus;
 * Excellent communication and collaboration abilities, particularly in cross-functional team environments.

## Description

* Architect, design, and implement digital IP blocks and subsystems for our neuromorphic SoCs;
 * Translate high-level product and algorithmic requirements into RTL-level specifications and microarchitectures;
 * Own all front-end design activities including RTL coding (SystemVerilog/Verilog), simulation, synthesis, STA, and design documentation;
 * Collaborate with the verification team to review test plans and co-develop functional testbenches;
 * Draft timing constraints and interface closely with backend engineers during physical design and gate-level simulation;
 * Integrate third-party IP and contribute to SoC-level architecture and bring-up;
 * Apply low-power design techniques and optimize for PPA;
 * Work with cross-functional teams including algorithm, platform/firmware, applications, and analog design;
 * Mentor more junior engineers, contribute to code reviews, and elevate overall team's expertise.


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