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# Digital IC Design Verification Engineer

- **Company:** Snap Inc.
- **Location:** New York, NY, United States
- **Experience:** Expert
- **Salary:** $173,000.0 - $259,000.0
- **Contract:** Permanent contract
- **Skills:** Linux, Logic Synthesis of Circuits, Transistor, Perl (Programming Language), Python (Programming Language), Cadence Virtuoso, Shell Script, Signal Integrity, Tcl (Programming Language), Linux Virtual Server, Digital Access Carrier System, Application Specific Integrated Circuits, Physical Design
- **Published:** October 8, 2026
- **Apply:** https://startup.jobs/digital-ic-design-verification-engineer-snap-inc-10327082

## About the Role

* Strong working knowledge of custom (transistor-level) layout, including matching techniques
 * Strong working knowledge of Cadence Virtuoso (Layout and Schematic) tool suite
 * Strong working knowledge of Mentor/Siemens Calibre tool suite (DRC, LVS, Extraction)
 * Scripting and automation, such as TCL, SKILL, Perl, Python and Shell scripts in Linux environment
 * Experience and capability to execute project tape out verification including DRC, ERC and LVS
 * Extensive understanding of signal integrity, reliability, layout effects (EM, IR drop) and other considerations
 * Knowledge of tool flows and techniques for achieving foundry DFM requirements
 * Track record of prior detailed design and custom layout experience of various types of designs such as SRAM, level shifters, IO design (ESD, latch-up), PLLs, Bandgaps, ADCs, DACs and amplifiers., * BSEE or relevant years of experience
 * 5+ years in directly applicable work performing custom layout
 * Optional - see preferred Qualifications

Preferred Qualifications:

 * Detailed understanding of 22nm and below CMOS foundry design node rules and requirements.
 * Experience with both Analog and Memory layouts
 * Excellent technical, documentation and verbal skills working with engineering and management teams
 * Knowledge of ASIC IC test and characterization
 * Understanding of digital design and place and route principles

## Description

* Work closely with digital and analog logic, circuit and physical design engineers & other custom layout engineers
 * Perform cell and block layout of Analog and Mixed-Signal circuit functions, meeting design rules and performance
 * Craft reusable scripts and methodologies that help automate design flow, repeatability and efficiency
 * Implement circuit layout strategies for optimal area, performance and power goals.
 * Support IC floor planning and place & route of full chip digital designs with digital and analog IP
 * Provides schedule, and cost inputs to program management
 * Create and present design documentation for internal design reviews
 * Execute parasitic extraction of circuit layout and iterate design improvements