> Markdown version of [/jobs/ext/3655531-senior-fpga-engineer](https://www.wearedevelopers.com/jobs/ext/3655531-senior-fpga-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior FPGA Engineer - **Company:** Evona, Inc. - **Location:** Medina, WA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Code Review, Continuous Integration, Extract Transform Load (ETL), Digital Technology, Embedded Software, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Signal Processing, Static Timing Analysis, Universal Asynchronous Receiver/Transmitter, Verilog, VHSIC Hardware Description Language (VHDL), Storage Devices, Serial Peripheral Interface, Git, Physical Design, Software Version Control - **Published:** October 9, 2026 - **Apply:** https://www.disabledperson.com/jobs/75929276-senior-fpga-engineer ## About the Role This position is ideal for an experienced engineer who can independently own complex projects, make sound architectural decisions, and deliver high-quality solutions on schedule in a fast-moving start-up environment., * At least 8 years of embedded firmware development experience, ideally involving radar or other mission-critical systems. * Strong RTL design experience using Verilog and/or VHDL, including work on satellite or aerospace applications. * Hands-on experience bringing up and verifying RTL-based designs on target hardware. * Experience integrating FPGA or SoC designs, including synthesis, place and route, and timing analysis. * Familiarity with low-speed interfaces such as I2C, SPI, UART, and RS-422. * Ability to read and interpret electrical schematics. * Experience with Git, CI pipelines, code reviews, and version-control workflows. * Ability to work independently, stay organized, and deliver in a lean, rapidly evolving environment. Preferred Experience Experience in any of the following areas would be valuable: * Distributed digital system design and implementation. * Clock-domain crossing and timing closure. * AMD UltraScale+ platforms. * High-speed ADC and DAC interfaces, including JESD204. * Signal-processing algorithm implementation in RTL. * Embedded architectures involving multiple FPGAs and peripheral interfaces such as SPI, UART, GPIO, I2C, and Ethernet. * Efficient, low-latency data movement between FPGAs, processors, storage devices, and networking interfaces. * Ethernet and TCP/IP networking stacks. * Radar, satellite, aerospace, or other high-reliability applications. * Eligibility and ability to obtain and maintain a Top Secret security clearance. You do not need to meet every listed qualification. Engineers with strong FPGA fundamentals, relevant mission-critical development experience, and the ability to learn quickly are encouraged to apply. ## Description * Partner with a multidisciplinary engineering team to define and refine firmware requirements. * Architect, design, and implement embedded firmware for a radar sensor payload. * Develop control and signal-processing functions in Verilog or VHDL. * Evaluate implementation complexity, maintainability, and FPGA resource requirements, including logic cells, embedded memory, and DSP slices. * Produce technical trade studies to support architecture and implementation decisions. * Integrate RTL designs onto FPGA and SoC platforms through synthesis, place and route, timing analysis, and timing closure. * Lead bring-up, verification, and validation of FPGA designs on prototype and flight hardware. * Collaborate with radar algorithm, electrical, software, and mechanical engineers to build dependable embedded systems. * Support the recruitment, interviewing, and hiring of additional engineering team members.