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# Memory System Designer and Place and Route Engineer

- **Company:** Broadcom
- **Location:** Saint Paul, MN, United States
- **Experience:** Expert
- **Salary:** $109,700.0 - $175,500.0
- **Contract:** Permanent contract
- **Skills:** Automation of Tests, Software Debugging, Python (Programming Language), Subsystems, Verilog, Linux Virtual Server, Virtual Memory, Physical Design
- **Published:** October 9, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3426226518&tx=DT11808UHD&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering., * Strong design skills

 * Ability to write and debug Verilog RTL code
 * Place and route expertise
 * Proficient in running STA, DRC, EM/IR tools, and attaining design closure
 * Ability to code in Python
 * Good understanding of synthesis tools and running synthesis
 * Capable of running and debugging logical equivalency checkers
 * Familiar with memory behavior
 * Proficient in writing automation scripts, and tools savvy
 * Good communication, interpersonal, and leadership skills
 * Motivated, self-driven, and good at multitasking

## Description

* Architect and design memory subsystems
 * Implement RTL of subsystem designs
 * Place and route (physical design)
 * Design closure: timing, DRC, LVS, EM/IR, etc.
 * Gate netlist synthesis