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# SMTS ASIC Digital Design

- **Company:** GF U.S. Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Code Coverage, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Failure Mode Effects Analysis, Field-Programmable Gate Array (FPGA), Python (Programming Language), Requirements Management, Reduced Instruction Set Computing, System on a Chip, SystemVerilog, Tcl (Programming Language), Verilog, Jama (Software), Application Specific Integrated Circuits, Caching
- **Published:** October 10, 2026
- **Apply:** https://globalfoundries.wd1.myworkdayjobs.com/External/job/Austin/SMTS-ASIC-Digital-Design_JR-2605618

## About the Role

* Master's or Bachelor's degree in Electrical/Electronic Engineering, Computer Engineering or a related field.
 * 8+ years of ASIC/SoC design or verification experience, with substantial time spent on functional safety.
 * Understanding of FMEDA, DFMEA and DFA for complex digital IP.
 * Understanding with SoC-level integration and system-level safety concepts.
 * Ability to read and analyze RTL (Verilog/SystemVerilog) and reason about microarchitecture - pipelines, caches, register files, memories.
 * Understanding of processor architecture, and how safety mechanisms are realized within it.
 * Familiarity with synthesis and DFT results as inputs to safety analysis (area back-annotation, test coverage).
 * Strong debugging and troubleshooting skills.
 * Excellent communication skills, autonomy, and the ability to run several activities in parallel.

Preferred Qualifications:

 * Functional safety certification or formal training (ISO 26262 / IEC 61508).
 * Experience as a Safety Element out of Context (SEooC) supplier, or integrating SEooC IP into an SoC safety concept.
 * Fault simulation tooling (VC Z01X or equivalent) - we will train you on our specific flow.
 * Scripting and automation (Python, TCL) - our FMEDA flow is script-driven.
 * Simulation and debug tools (VCS, Verdi); FPGA design flow.
 * Requirements management tooling (Jama) and safety traceability practice.
 * Low-power design and UPF.
 * ISO/SAE 21434 cybersecurity, or IEC 61508 in industrial applications.
 * Experience with automotive tier-one customers.
 * RISC-V architecture.

## Description

* Own hardware safety analysis for processor IP configurations: FMEDA, DFMEA, DFA and FTA, through to external assessment.
 * Perform SoC-level safety analysis for Custom Silicon programs: integration of safety elements, system-level FMEDA, and the safety concept at the SoC boundary.
 * Analyze dependent failures and freedom from interference across IP boundaries within an SoC.
 * Derive and track safety metrics (SPFM, LFM, PMHF) and drive diagnostic coverage improvement together with the STL and verification teams.
 * Define and review safety mechanisms at RTL level - ECC, parity, lockstep, register protection, watchdog - and verify they meet the claimed diagnostic coverage.
 * Plan and interpret fault injection campaigns, and reconcile fault simulation results against the FMEDA.
 * Produce and maintain safety work products: safety manual, safety analysis reports, safety case contributions, and assumptions of use.
 * Maintain traceability from safety requirements through design to verification evidence.
 * Support ISO 26262 assessments and respond to customer technical questions on safety architecture and analysis.

Other Responsibilities:

 * Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.