> Markdown version of [/jobs/ext/3670095-asic-soc-verification-engineer](https://www.wearedevelopers.com/jobs/ext/3670095-asic-soc-verification-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# ASIC/SoC Verification Engineer

- **Company:** Epitec, Inc.
- **Location:** El Segundo, CA, United States (Remote available)
- **Experience:** Expert
- **Salary:** $226,720.0 - $263,661.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Beamforming, C++ (Programming Language), Computer Engineering, Modems, Software Debugging, Formal Verification, Regression Testing, Specman, Subsystems, SystemVerilog, Application Specific Integrated Circuits, Large Language Models
- **Published:** October 10, 2026
- **Apply:** https://www.dice.com/job-detail/6d02cf31-088e-4481-a6fa-176b423b5741

## About the Role

* Bachelor's degree in Electrical Engineering, Computer Engineering, or a related engineering discipline, or comparable professional experience
 * Approximately 7+ years of ASIC, SoC, RTL, or complex digital functional verification experience preferred
 * Strong hands-on experience with SystemVerilog and UVM
 * Experience developing or significantly contributing to verification environments and testbenches
 * Strong understanding of verification planning and metric-driven verification
 * Experience with:
 + Functional coverage
 + Assertions
 + Coverage closure
 + Regression testing
 + RTL and waveform debugging
 * Ability to independently investigate complex verification failures and drive them to root cause
 * Ability to take ownership and operate effectively when requirements or specifications are still evolving

Highly Desired Experience
Experience in one or more of the following would be highly valuable:

 * C/C++ verification or modeling
 * Formal verification
 * Hardware emulation
 * Processor-driven SoC verification
 * CPU subsystem verification
 * Networking ASICs or NoC/interconnect verification
 * Modem or baseband verification
 * Digital signal processing (DSP)
 * Beamforming
 * Wireless communications
 * RF signal verification
 * Satellite communications
 * LDPC, FEC, framing, or fixed-point analysis
 * ECC, redundancy, fault injection, or reliability verification
 * AI/ML/LLM-assisted verification tools or workflows, The strongest candidate is a Senior ASIC/SoC Verification Engineer who has built UVM-based verification environments from the ground up and independently owned verification from planning through coverage closure and sign-off.
You don't necessarily need satellite or wireless experience. If you come from a strong semiconductor, processor, networking, modem, or custom silicon environment and have the verification fundamentals to jump into a new program with limited ramp-up, we want to hear from you.

## Description

We are seeking an experienced Senior ASIC/SoC Verification Engineer to support the development of a next-generation custom silicon platform for an advanced satellite communications network.
This is a unique greenfield verification opportunity. Rather than stepping into a mature verification environment, you will help define and build the verification strategy, methodology, testbenches, and infrastructure for a new silicon program.
The technology includes a high-throughput modem and DSP-intensive digital beamforming architecture, with verification work spanning IP, subsystem, and full SoC levels. You will have the opportunity to take significant ownership of your area and influence how verification is performed as the team and program continue to grow.
Candidates with modem, DSP, wireless, RF, networking, or satellite communications experience are highly desirable, but deep verification expertise and the ability to work independently are more important than specific domain experience.
What You'll Do

 * Own ASIC/SoC verification activities for complex digital blocks and subsystems from test planning through sign-off
 * Build SystemVerilog/UVM testbenches and verification environments from scratch
 * Translate evolving design specifications into detailed verification strategies, test plans, and measurable coverage goals
 * Develop verification components including scoreboards, monitors, assertions, coverage models, reference models, and reusable testbench components
 * Perform constrained-random, directed, formal, and system-level verification
 * Debug complex RTL, datapath, control logic, testbench, and system-level failures
 * Drive functional coverage closure, regression health, and verification sign-off
 * Help develop reusable verification infrastructure, regression environments, and CI workflows across IP and SoC levels
 * Support processor-driven and C/C++-based verification where applicable
 * Evaluate and apply AI-assisted verification techniques for stimulus generation, regression triage, and coverage analysis
 * Partner closely with ASIC designers, architects, modeling engineers, and other verification engineers
 * Review verification architectures and help mentor less-experienced engineers