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# Senior FPGA Engineer

- **Company:** Job Impulse
- **Location:** Redondo Beach, CA, United States
- **Experience:** Expert
- **Salary:** $145,000.0 - $200,000.0
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Software Debugging, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), Hardware Description Language, MATLAB, Signal Processing, Static Timing Analysis, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Fpga Hardware, State Machines, Parallel Computation, Physical Design
- **Published:** October 10, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=ca0da47f12ef2a8b

## About the Role

* Bachelor's degree in Electrical Engineering, Optical Engineering, or related technical discipline.
 * Minimum 5+ years of experience in the optical communications field
 * Expertise in HDL development using VHDL or Verilog
 * Experience with high-speed digital design, timing closure, and parallel data path architectures
 * Familiarity with AXI4/AXI-Stream interface standards
 * Proficiency with Xilinx (Vivado) and Intel/Altera (Quartus) FPGA toolchains
 * Experience with FPGA clocking resources (PLL, MMCM) and multi-clock domain integration
 * Strong understanding of digital logic, state machines, pipelining, and data-path design
 * Ability to create and maintain self-checking testbenches for module-level and system-level verification
 * Hands-on experience with lab debugging and FPGA hardware bring-up, * 3+ years of experience implementing DSP algorithms in hardware
 * 3+ years of experience with advanced communication systems or signal-processing architectures
 * Familiarity with MATLAB/Simulink for algorithm modeling and hardware mapping
 * Self-motivated with proven ability to communicate technical challenges, explain rationale and resolve critical issues
 * Experience in a startup or fast paced agile development environment

## Description

* Develop, implement, and optimize FPGA designs using VHDL or Verilog
 * Perform high-speed digital integration, including multi-clock domain interfaces, timing closure, and advanced clock-constraint management
 * Architect FPGA data paths with an emphasis on throughput, parallelism, and resource efficiency
 * Implement and integrate AXI4/AXI-Stream interfaces and related on-chip bus architectures
 * Design and manage FPGA clocking using PLL and MMCM primitives
 * Use Xilinx and Intel/Altera FPGA tools for synthesis, place-and-route, constraint definition, and timing analysis
 * Build self-checking testbenches for functional verification and regression coverage
 * Debug FPGA designs in the lab using logic analyzers, oscilloscopes, and FPGA debug tools such as Chipscope or SignalTap
 * Collaborate with DSP, systems, and software teams to define hardware architectures and support algorithm implementation